作者finalhaven (爆炸神威)
看板comm_and_RF
標題[問題]VERILOG一問
時間Fri May 16 00:06:57 2008
module led_rat(clkin,reset,led);
input clkin;
input reset;
output [7:0]led;
reg [23:0]q;
reg [7:0]led;
reg div_clkout;
reg flag;
always@( posedge reset or negedge clkin)
begin
if(reset)
begin
div_clkout = 0;
q = 0;
end
else if (q == 50000000)
begin
div_clkout = ~div_clkout;
q = 0;
end
else
q=q+1;
end
always@(posedge reset or negedge div_clkout)
begin
if(reset)
begin
led = 0;
flag = 0;
end
else if (flag == 0)
begin
led = led << 1;
flag = 1;
end
else if (flag == 1)
begin
led = led >> 1;
flag = 0;
end
else
led = led;
end
endmodule
這個程式主要是做除頻+LED移位的功能
可是合成完之後，會找不到CLK的腳位
有大大可以幫我看一下嗎?謝謝
以下是timing report
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.317ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay: 9.317ns (Levels of Logic = 4)
Source: reset (PAD)
Destination: led<3> (PAD)
Data Path: reset to led<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 reset_IBUF (reset_IBUF)
LUT2:I0->O 2 0.479 0.915 _n00001 (flag)
LUT3:I1->O 4 0.479 0.779 led<1>1 (led_1_OBUF)
OBUF:I->O 4.909 led_3_OBUF (led<3>)
----------------------------------------
Total 9.317ns (6.582ns logic, 2.735ns route)
(70.6% logic, 29.4% route)
=========================================================================
--
當在跑向終點的漫長旅程上，請不要忘記最初起點的夢想!
--
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◆ From: 220.133.46.8
※ 編輯: finalhaven 來自: 220.133.46.8 (05/16 00:14)
1F：推 yyuto:你的CLK是設哪個參數 clkin? 61.64.235.177 05/16 00:37
2F：→ finalhaven:對呀～ 220.133.46.8 05/16 01:16