作者iceclub (火爆阿浪)
站內PLT
標題[問題] VHDL的錯誤問題
時間Wed Oct 10 12:43:32 2007
剛剛再跑VHDL時
從範例抄下的題目
跑的時候出現一個錯誤
Error (10500): VHDL syntax error at test.vhd(7) near text "END"; expecting
an identifier ("end" is a reserved keyword), or "constant", or "file", or
"signal", or "variable"
原始程式碼是
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--Simple module that connects the SW switches to the LEDR lights
ENTITY part1 IS
PORT (SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);--red LEDs
END part1;
ARCHITECTURE Behavior OF part1 IS
BEGIN
LEDR <= SW;
END Behavior;
請各位大大
幫我檢查一下
到底是什麼問題
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 218.165.111.161
1F：推 CuckooBoy:看樣子都沒有錯耶..... 11/17 21:59
2F：→ BasilC:port (SW : ...... ); 少加一個")" 03/05 15:47