作者iceclub (火爆阿浪)
站内PLT
标题[问题] VHDL的错误问题
时间Wed Oct 10 12:43:32 2007
刚刚再跑VHDL时
从范例抄下的题目
跑的时候出现一个错误
Error (10500): VHDL syntax error at test.vhd(7) near text "END"; expecting
an identifier ("end" is a reserved keyword), or "constant", or "file", or
"signal", or "variable"
原始程式码是
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--Simple module that connects the SW switches to the LEDR lights
ENTITY part1 IS
PORT (SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);--red LEDs
END part1;
ARCHITECTURE Behavior OF part1 IS
BEGIN
LEDR <= SW;
END Behavior;
请各位大大
帮我检查一下
到底是什麽问题
--
※ 发信站: 批踢踢实业坊(ptt.cc)
◆ From: 218.165.111.161
1F：推 CuckooBoy:看样子都没有错耶..... 11/17 21:59
2F：→ BasilC:port (SW : ...... ); 少加一个")" 03/05 15:47