※ [本文轉錄自 NTUGIEE_ric 看板] 作者: ric2k1 (Ric) 看板: NTUGIEE_ric 標題: Re: [動員令] 12/27 (三) Prof. Sakallah's talk 時間: Mon Dec 25 22:19:18 2006 聽過 GRASP, MINCE, AMUSE, Satire, PBS, Peublo... 嗎 ? 沒錯, 這些知名的 tools 都是由 Prof. Sakallah 的實驗室出來的, 所以他的演講必定不可錯過!! 有上 Testing 課的同學也可以來聽喔~~~ 有跟李建模老師協調過了, 星期三的課將會以 ICS 組的同學的專長為主... 早上 9 點開始演講!!!! 請提早入場!!!! 地點: BL 201 ※ 引述《ric2k1 (Ric)》之銘言： 大師參訪, 老師負責接待, 學生務必要早起聽演講 !!!! 不知道他是誰, google 一下吧... (聽說下學期還有 Prof. Sharad Malik...) ----- Satisfiability and Design Verification Boolean satisfiability (SAT) solvers are playing an increasingly larger role in the verification step of the hardware design process. This is primarily due to the tremendous progress in their performance and capacity over the last ten years. In this tutorial, I will cover the basics of SAT solving, and illustrate the use of scalable Boolean reasoning in an abstraction-based microprocessor verification system. Time permitting, I will touch upon satisfiability modulo theories (SMT) which augments Boolean SAT with more expressive constraints leading to further improvements in performance and scale. Bio: Karem A. Sakallah (S'76-M'81-SM'92-F'98) received the B.E. degree in electrical engineering from the American University of Beirut, Beirut, Lebanon, in 1975, and the M.S.E.E. and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, in 1977 and 1981, respectively. In 1981, he was with the Department of Electrical Engineering at Carnegie Mellon University as a Visiting Assistant Professor. From 1982 to 1988, he was with the Semiconductor Engineering Computer-Aided Design Group at Digital Equipment Corporation in Hudson, MA, where he headed the Analysis and Simulation Advanced Development Team. Since September 1988, he has been with the University of Michigan, Ann Arbor, as a Professor of Electrical Engineering and Computer Science. From September 1994 to March 1995, he was with the Cadence Berkeley Laboratory in Berkeley, CA, on a six-month sabbatical leave. He has authored or coauthored more than 200 papers and has presented seminars and tutorials at many professional meetings and various industrial sites. His current research interests include the area of computer-aided design with emphasis on logic and layout synthesis, Boolean satisfiability, discrete optimization, and hardware and software verification. Dr. Sakallah was an Associate Editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS from 1995 to 1997 and has served on the program committees of the International Conference on Computer-Aided Design, Design Automation Conference, and the International Conference of Computer Design as well as numerous other workshops. He is currently an Associate Editor of the IEEE TRANSACTIONS ON COMPUTERS. He is a fellow of the IEEE and a member of the ACM and Sigma Xi. --

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