作者hunter0904 (態度)
看板Grad-ProbAsk
標題[理工][記組]99成大電機
時間Sun Feb 6 23:14:24 2011
True or false:
(a)Pipeling instruction cache access improves the instruction throughput
rather than individual instruction fetch latency.
(b)Pipeling instruction cache access improves the instruction throughput
other than individual instruction fetch latency.
(c)A load-use data hazard occurs because the pipeline flushes
the instructions behind.
老師題庫班答案是寫三個false 但是講義是a true 其他false
我也看不太懂a,b所述敘的東西
請高手幫忙回答 感恩
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◆ From: 122.126.125.52
1F：推 fj91611:A是改善throughput不改善latency B是兩者都改善 02/07 00:23
2F：→ fj91611:有錯請糾正我XD 02/07 00:24
3F：→ hunter0904:other than 的意思是 除了? 02/07 08:18
4F：推 xygod:我覺得TFF 02/07 17:31