作者hunter0904 (态度)
看板Grad-ProbAsk
标题[理工][记组]99成大电机
时间Sun Feb 6 23:14:24 2011
True or false:
(a)Pipeling instruction cache access improves the instruction throughput
rather than individual instruction fetch latency.
(b)Pipeling instruction cache access improves the instruction throughput
other than individual instruction fetch latency.
(c)A load-use data hazard occurs because the pipeline flushes
the instructions behind.
老师题库班答案是写三个false 但是讲义是a true 其他false
我也看不太懂a,b所述叙的东西
请高手帮忙回答 感恩
--
※ 发信站: 批踢踢实业坊(ptt.cc)
◆ From: 122.126.125.52
1F：推 fj91611:A是改善throughput不改善latency B是两者都改善 02/07 00:23
2F：→ fj91611:有错请纠正我XD 02/07 00:24
3F：→ hunter0904:other than 的意思是 除了? 02/07 08:18
4F：推 xygod:我觉得TFF 02/07 17:31