作者bernachom (Terry)
看板Grad-ProbAsk
標題[問題] 計組－管線指令
時間Sat May 9 00:54:36 2009
請教一下
Schedule the following instruction segment into a superscaler
pipeline for MIPS. Assume that the pipeline can execute one ALU Or
branch instruction and one data transfer instruction concurrently.
For the best, the instruction segment can be executed in four clock
cycles. Fill in the instruction identifiers into the table.
NOte that data dependency should be taken into account.
(Identifier) (Instruction)
In-1 loop: lw $t0.0($1)
In-2 addu $t0.$t0.$s2
In-3 sw $t0.0($1)
In-4 addi $s1.$s1,-4
In-5 bne $s1.$zero.Loop
＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿
▕clock ▕ alu or branch instruction ▕data transfer instruction ▕
▕＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿
▕1＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕
▕2＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕
▕3＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕
▕4＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕
表格我盡力了...不會畫...
麻煩了，謝謝
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◆ From: 61.228.97.36
※ 編輯: bernachom 來自: 61.228.97.36 (05/09 00:55)
1F：→ uminchu185: lw $t0,0($1) 05/09 10:05
2F：→ uminchu185:addi,$s1,$s1,-4 05/09 10:06
3F：→ uminchu185:addu $t0,$t0,$s2 05/09 10:06
4F：→ uminchu185:bne $s1,$0,Loop sw $t0,4($s1) 05/09 10:08
5F：→ uminchu185:I4往前移消除hazard,因此I3的參考位址需加4 05/09 10:15
6F：→ bernachom:謝謝您^^ 05/09 14:30
7F：推 whisp1222:樓上要不要找人一起念 一起念有問題才能互相討論 否則你 05/09 17:19
8F：→ whisp1222:光打字就打很久吧 而且有朋友一起念比較久 05/09 17:20
9F：→ icrts:比如說樓上就不錯喔 XD 05/09 21:32
10F：→ bernachom:有在想啦，不過目前先把底子加強一下，謝謝各位嚕^^ 05/09 23:31