作者s552400 (<(_ _)>請多指教)
站內Electronics
標題[問題] VLSI設計
時間Sat Jan 12 00:05:49 2008
Please design a divided-by-8 frequency divider with three cascaded DFFs as
shown below. The clock frequency is 1MHz. Please show:
1.Schematic of the DFF.
2.Waveforms to verify the function of DFF.
3.Simulation waveforms for CLK, Q1, Q2 and Q3.
4.Layout and post-simulation results.
__________________ ___________________ ___________________
| ___________ | | ___________ | | ___________ |
| | | | | | | | | | | |
|__| D Q | | |___| D Q | | |___| D Q | |
| Q1 | | | Q2 | | | Q3 | |
| _ | | | _ | | | _ | |
CLK--> |> Q |___|------|> Q |___|------|> Q |___|
|___________| |___________| |___________|
這是期末project,但h-spice程式部份不知如何著手.
想求點提示
謝謝
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◆ From: 163.25.118.141
1F：推 jingwoei:去查DFF相關的文獻吧…有很多。 01/12 00:24
2F：→ oorr:divider-8 01/12 13:56
3F：→ ckl12345:這當期末project,也太簡單了點,課本上的東西*3而已 01/13 11:45
4F：推 OnepieceZoro:一個非同步的counter 01/13 12:34
5F：→ s552400:老師請助教花3hr教基本用法後就要我們做出這,也沒用課本.. 01/13 17:43
6F：→ s552400:所以對我們而言這很困難 01/13 17:46
7F：推 justtyler9:先把latch組起來,再組成dff 01/13 18:35