作者dot40431 (點點)
看板Electronics
標題[問題] 用Verilog-XL compile出來的錯誤
時間Thu May 3 12:28:47 2007
Compiling source file "add_sub.v"
Compiling source file "add_sub.v"
Error! Module name (ADD_SUB) previously declared [Verilog-MNPD]
"add_sub.v", 1:
Error! Module name (testbench) previously declared [Verilog-MNPD]
"add_sub.v", 16:
2 errors
End of Tool: VERILOG-XL 05.50.003-p May 3, 2007 12:25:47
請問有沒有人知道這是什麼錯誤呢?辜狗辜不到耶QQ
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1F：推 tkhan:閱.. 05/03 14:53
2F：推 bighead319:錯誤訊息不是說的很清楚了=>重複宣告 05/12 03:06