作者dot40431 (点点)
看板Electronics
标题[问题] 用Verilog-XL compile出来的错误
时间Thu May 3 12:28:47 2007
Compiling source file "add_sub.v"
Compiling source file "add_sub.v"
Error! Module name (ADD_SUB) previously declared [Verilog-MNPD]
"add_sub.v", 1:
Error! Module name (testbench) previously declared [Verilog-MNPD]
"add_sub.v", 16:
2 errors
End of Tool: VERILOG-XL 05.50.003-p May 3, 2007 12:25:47
请问有没有人知道这是什麽错误呢?辜狗辜不到耶QQ
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◆ From: 140.114.86.101
1F：推 tkhan:阅.. 05/03 14:53
2F：推 bighead319:错误讯息不是说的很清楚了=>重复宣告 05/12 03:06