Designing without a net: Restricted design rules challenge DFM's role EE Times (07/24/2006 9:00 H EST) This week's Design Automation Conference will make it clear that the EDA industry is counting on design-for-manufacturability (DFM) for a much-needed boost. But the restricted design rules (RDRs) that are quietly emerging for 45-nanometer and smaller geometries may reduce the need for some DFM tools and techniques, some observers say. The RDR concept is surfacing from universities and IDM research labs and appears headed for a prominent role at 45 nm and below. The idea is to enhance manufacturability by restricting the layouts designers produce. For example, RDRs may set limitations on gate pitch and orientation, or even mandate that all gate-forming polysilicon features have the same orientation, width and pitch. Depending on how restricted the RDRs are, the result could be regular structures reminiscent of gate arrays or programmable-logic arrays (PLAs). The compelling argument is that creating design layouts using only regular features will improve lithographic printability and make resolution enhancement technology easier to implement. But very regular structures also carry potential area and performance penalties, causing some to argue that "extreme" RDRs, such as single-pitch, single-orientation rules, are unlikely to be adopted. Most observers agree that some level of restriction seems inevitable. "All fabs are pursuing some form of RDRs at 45 nm," said John Lee, general manager of the physical-verification business unit at Magma Design Automation Inc. "Not all are equally restrictive, but all enforce regularity." "What people are talking about is very regular structures, primarily in the active-device domains," said Ted Vucurevich, chief technology officer at Cadence Design Systems Inc. "This takes us back to the old days, in a sense, where you had gate array types of architectures and regularity of those structures." RDRs have been proven out in a 45-nm design by IBM and are under advanced-stage development at other major chip makers, including Intel Corp., Advanced Micro Devices Inc. and Toshiba Corp., according to Gary Smith, chief EDA analyst at Gartner Dataquest. RDRs appear to be a shoo-in for at least some logic devices at 32 nm, according to Smith, who spoke on the topic at the Semicon West conference in San Francisco two weeks ago. "It looks very promising," Smith said. "This is something that we are going to see a lot of." The use of RDRs will not make DFM tools obsolete, he said, but it definitely "limits the market for DFM." 'Dirty secret' "RDRs are the dirty secret that DFM companies do not talk about, because strong RDRs may obviate the need for DFM," said Magma's Lee. The right solution, he said, is to augment RDRs with a physical-implementation system that includes lithography models, statistical timing and power, and correction and signoff with a physical-design tool. Most observers see RDRs and DFM as largely complementary. That's the case at IBM, which has done much of the pioneering work in this area. "RDRs do not eliminate the need for the model-based DFM techniques currently being discussed in the EDA industry," said Paul Farrar, vice president of process development at IBM's Semiconductor Research and Development Center. "When properly implemented, RDRs, in conjunction with model-based DFM, can simultaneously maintain design efficiency, schedule integrity and manufacturability. We have shown this on a leading-edge, high-performance 65-nm product." As professor of computer science and engineering at the University of California at San Diego (UCSD), Andrew Kahng has published research on RDRs. And as CTO of DFM startup Blaze DFM Inc., Kahng does not believe that RDRs will make DFM unnecessary. "Some aspects of DFM, such as closing the loop back from lithography simulation to device-level simulation, may become less critical," he said. "Other types of variability--reticle- and wafer-level biases, or misalignment distributions, for example--will remain a concern." Kahng acknowledged that "extreme" RDRs, such as mandating only one pitch and orientation, would in fact "reduce the pressure" on DFM. But he believes such stringent measures aren't likely to take root, because of area and performance trade-offs. "DFM technology and tools should be kept in the picture with RDRs," he said. "They can dramatically reduce the degree of draconian rules you need." Predictably, executives from major EDA vendors downplayed the potential for RDRs to wipe out the DFM market. "While we see RDRs as a way to mitigate manufacturing issues, they are only one component, and they will certainly not lessen the need for a comprehensive DFM approach," said Srinivas Raghvendra, senior director of DFM solutions at Synopsys Inc. "Some things are going to be easier [with RDRs], but I don't think people will dramatically change the tools and technologies they use to get chips out," said Cadence's Vucurevich. He further cautioned that RDRs are not a done deal. "This is one approach, presuming that lithographic processes do not change significantly as we get down to 32 or 22 nm," he said. "If there's a change or improvement in the lithographic process, I don't see [RDRs] as a direction we'll necessarily take." RDRs are just another element in the "bag of tricks" for dealing with manufacturability issues, said Wally Rhines, Mentor Graphics CEO. "There will be more DFM in every [process] generation, independently of what happens with other design approaches," Rhines said. From scorn to acceptance The future did not always look so bright for RDRs and related methodologies that emphasize regular structures. According to early researchers in this area, chip makers originally turned up their noses at RDRs, quickly dismissing the technology because of a perceived need to sacrifice area and performance. Robert Brayton, a processor of electrical engineering and computer sciences at the University of California, Berkeley, co-authored a book on structured regular silicon with former student Fan Mo (now with Synplicity Inc.). Brayton said chip makers initially showed no interest in his research during the late 1990s and early part of this decade. "They weren't willing to give up the area and delay," he said. Larry Pileggi, Tanoto professor of electrical and computer engineering at Carnegie Mellon University (Pittsburgh) and director of the school's Center for Silicon System Implementation, has been conducting research on chip design using regular features since 1997 as part of a project for the university-based Microelectronics Advanced Research Corp. Back then, Pileggi said, some of the research group's member companies were perplexed about the point of the research. But times have changed. Pileggi said he and his team have done research that proves the concept of regular design features at 65 nm with no area or performance penalty by changing the way synthesis is done and the way logic circuits are configured. Everybody was thinking that if you 'go regular,' you have to pay a penalty," Pileggi said. "Nobody wants to pay that penalty until you have to. That's what we've shown--that you can do it without paying that penalty." Published research Papers on the benefits and trade-offs of RDRs have been presented at conferences in recent years. IBM researchers, for example, described RDR work in a paper given at the International Conference on Computer-Aided Design (ICCAD) in 2004. The paper described a project called LG3O (Layout using Gridded Glyph Geometry Objects). The restrictions proposed in the paper included requiring that gate-forming polysilicon features have the same orientation and width, and that they be placed at a fixed pitch. IBM's approach is to extend those restrictions on polysilicon features to all layers of a design, then tailor the layout flow and tools to take advantage of the restrictions. IBM's experiments with 65-nm designs showed that LG3O does not impose much more restriction than the technology requirements themselves, according to the authors. Farrar noted that IBM is evaluating the LG30 methodology now in an internal product design. Indeed, he said, IBM already has restrictions on gate pitch and orientation at the 65-nm process node. While the goal is to achieve more-regular designs, he noted, "RDRs do not necessarily lead to gate array- or PLA-like design." Possible RDR candidates: 1) bent gate 'on' as baseline, 2) poly-to-poly spacing, poly-to-diffusion spacing, 4) poly line end extension and 5) bent gate line width. Kahng co-authored a technical paper on RDR trade-offs that was presented at the Design Automation Conference in 2004. The paper was part of a Semi- conductor Research Corp. project that was jointly conducted UCSD and the University of Michigan, with collaboration from Luigi Capodieci, principal member of the technical staff Advanced Micro Devices Inc. The research had focused on four RDRs, Kahng said. One was avoidance of bent gates, which is generally prohibited anyway these days. The others involved design rules for poly-to-poly minimum spacing, line-end extension and poly-to-diffusion minimum spacing. The paper found that small increases in the minimum allowable polysilicon line-end extension can provide high levels of immunity to lithographic defocus conditions. The authors had also found that modifying the minimum field polysilicon-to-diffusion spacing could provide better manufacturability. The authors demonstrated data volume reductions of 20 to 30 percent relative to a baseline "flexible" rule set, and reductions of nearly 50 percent in worst-case edge placement errors, from that set of basic RDRs. They reported that the penalty was only 0 to 5 percent in area and "a few percent in delay at most." Others agree the penalties aren't large. "The expected drawback is that devices will be larger and there will be a performance hit," said Gartner's Smith. "But chip makers can't run these chips as fast as they want to, anyway, because of heat dissipation." Cadence's Vucurevich said there probably won't be an area or performance penalty, so long as the restricted design rules apply to the device layers. "If you start talking about RDR patterns for interconnect, all bets are off," the Cadence CTO said. "Anytime you try to take away freedom from the designers, they are going to rebel," said Pileggi of Carnegie Mellon. "But I don't think that it's really true that moving to regular features stifles creativity. "The design freedom is moving to a different level, and designers will need to find different ways to be creative." http://tinyurl.com/tmy5b --

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