[公司名稱] Sintegra Inc. [職缺] Physical Design Engineer (APR) – Hsinchu [工作內容] * ASIC/SoC Physical Design implementation from Netlist to GDSII * Floorplanning and Power Planning * Placement and optimization * Clock Tree Synthesis (CTS) * Routing and post-route optimization * Static Timing Analysis (STA) and Timing Closure * Setup/Hold analysis and optimization * ECO implementation and timing fixes * Signal Integrity (SI) analysis * IR Drop / EM analysis and optimization * Physical verification including DRC/LVS * PPA (Power, Performance, Area) optimization * Collaborate with RTL, STA, DFT and other design teams * Support final design signoff and tapeout [工作地點] 竹北 [職務需求] * 2–6 years of hands-on ASIC Physical Design / APR experience * BS/MS degree in Electrical Engineering, Electronics Engineering, Computer Engineering or related field * Good understanding of the complete Physical Design flow * Hands-on experience in one or more areas including Floorplan, Placement, CTS, Routing, STA, Timing Closure and ECO * Experience with advanced semiconductor process nodes preferred * Good understanding of timing, clocking, congestion and power optimization * Strong debugging and problem-solving skills * Ability to work independently and collaborate with global engineering teams [待遇] 年薪台幣 200萬 ～ 250萬元 [聯絡方式] 意者請將英文 CV 寄至： [email protected] --

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