作者nichaellin (章魚)
站內Programming
標題[問題] verilog基本簡單的updown counter
時間Sun Aug 5 17:40:01 2012
module Counter(clk,rst,slect,out);
input [1:0]slect;
input clk,rst;
output [9:0]out;
reg [9:0]out;
always@(slect)
begin
if(slect==2'd0)
always@(posedge clk)
begin
if(rst)
begin
out=10'd0;
end
else if(out==10'd1023)
begin
out=10'd0;
end
else
begin
out=out+1'd1;
end
end
if(slect==2'd1)
always@(posedge clk)
begin
if(rst)
begin
out=10'd1023;
end
else if(out==10'd0)
begin
out=10'd1023;
end
else
begin
out=out-1'd1;
end
end
if(slect==2'd3)
always@(posedge clk)
begin
if(rst)
begin
out<=10'd0;
end
else if(out!=10'd1023)
out<=out+1'd1;
end
else(out!=10'd0)
out<=out-1'd1;
end
end
end
end module
條件我假設是可以讓他
1.往上數到1023
2.往下數到0
3.0~1023~0這樣數
可是compile不過
我是新手一直苦無解答QQ
不知道有沒有人能幫幫我
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◆ From: 140.116.131.177
1F：推 mars90226:錯誤訊息是甚麼?125.226.179.171 08/05 18:36
2F：→ nichaellin:我把end module改成endmodule140.116.131.177 08/05 18:48
3F：→ nichaellin:就可以了耶XD140.116.131.177 08/05 18:48
5F：→ flarehunter:always裡面放always應該是不行的吧 140.112.41.107 08/09 17:53