作者jason543 (時間的眼淚)
看板Programming
標題[問題] 想請問VHDL的問題
時間Mon Sep 22 19:37:45 2008
小弟寫了一個小程式 但是不知道為啥跑圖時有一個INPUT跑不出來
是用Xilinx跑的
entity test is
port( data_in : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_out : out STD_LOGIC;
reg_data_out : out STD_LOGIC_VECTOR (6 downto 0));
end test;
architecture Behavioral of test is
begin
PROCESS (reset,clk)
variable reg_z1,reg_z2,reg_z3,reg_z4,reg_z5,
reg_z6,reg_z7 : STD_LOGIC;
variable reg_a1 : STD_LOGIC;
begin
if (reset = '0') then
reg_z1:='1';
reg_z2:='1';
reg_z3:='0';
reg_z4:='1';
reg_z5:='1';
reg_z6:='0';
reg_z7:='0';
reg_a1:='0';
reg_data_out<="0011011";
elsif ( clk 'event and clk='0') then
reg_a1:=reg_z4 xor reg_z7 xor data_in;
reg_z7:=reg_z6;
reg_z6:=reg_z5;
reg_z5:=reg_z4;
reg_z4:=reg_z3;
reg_z3:=reg_z2;
reg_z2:=reg_z1;
reg_z1:=reg_a1;
data_out<=reg_a1;
reg_data_out(0)<=reg_z1;
reg_data_out(1)<=reg_z2;
reg_data_out(2)<=reg_z3;
reg_data_out(3)<=reg_z4;
reg_data_out(4)<=reg_z5;
reg_data_out(5)<=reg_z6;
reg_data_out(6)<=reg_z7;
end if;
end PROCESS;
end Behavioral;
不知道為啥data_in 都沒有值
程式都沒有error出現!!
請指教 謝謝
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※ 編輯: jason543 來自: 140.126.131.62 (09/22 19:39)