Double Patterning Wrings More From Immersion Lithography Aaron Hand Semiconductor International Feb. 1 2007 Whether you are in the camp that believes extreme ultraviolet (EUV) is the only logical answer for next-generation lithography, or you think there must be another workable alternative out there, most are in agreement that optical lithography will need continued extensions for several years to come. Although some chipmakers say they can stretch dry lithography considerably further with more radical resolution enhancement techniques (RETs), such as stronger phase shifting, various illumination tricks and more, others will make the switch to immersion lithography somewhere around 45 nm. But even water-based immersion lithography is not enough to take production all the way to 32 nm half-pitch production — whether EUV lithography is introduced at that point or not. Several groups have, for some time, been exploring the feasibility of high-index immersion lithography — using immersion fluids, photoresists, and even lens elements with a higher refractive index to enable lens systems with even higher numerical apertures (NAs) than the 1.35 NA possible with water, thereby reducing the effective resolution of the lithography system. However, many in the industry are not convinced that high-index immersion will be able to give the necessary bang for the buck. Meanwhile, there is growing support for a different solution that would require less change to the current lithography infrastructure, and that could effectively bridge the gap to 32 nm, if not beyond. Double patterning, also known as double processing, is a solution that has been discussed in the past, but has only recently been seriously considered as a mainstream solution to the dangerously falling k1 factor — a figure that relates to the complexity of the lithography process. Double patterning effectively reduces the k1 factor to <0.25 (Fig. 1), which is considered to be the theoretical limit for single exposure. “Especially because establishing a new infrastructure is known to take time, this is why many companies today see double patterning as a potential intermediate solution, reducing the risks for delays, and introduction at 32 nm,” said Kurt Ronse, director of advanced lithography at IMEC (Leuven, Belgium). From a timing standpoint, double patterning is really the only thing available in the next couple of years, according to Gene Fuller, principal engineer at Nikon Precision Inc. (Belmont, Calif.). Ron Kool, director of product marketing at ASML (Veldhoven, Netherlands), also sees double patterning as the most logical bridge between standard immersion and EUV. Double patterning basically involves splitting a dense circuit pattern into two separate, less dense patterns that are then printed on a target wafer. “ You can do it lots of different ways, but I think what most people are looking at is straightforward, where you literally take the CAD layout and split it up in some intelligent manner,” Fuller said. Although there are variations of double patterning, the basic scheme is to print half the pattern, process it, bring it back to spin more resist on it, print the second half of the pattern, and finish up with the hard mask or underlying etch. IMEC has developed a gate patterning process using a hard mask approach, according to Ronse, testing the process on a 1.2 NA immersion scanner at ASML. Example results are shown in Figure 2. The hard mask has not been removed from the poly lines in one of the two exposures, making it easy to see which lines have been patterned using the first mask and which have been patterned using the second mask. “A k1 below 0.2, in fact, looks quite feasible, which even allows us to go to sub-32 nm double patterning technologies,” Ronse said. Using this baseline process, IMEC has been experimenting with double patterning on a number of typical flash and logic patterns. Unlike with the flash cells, some problems cropped up with logic patterns that related to stitching polygons back into their original circuit layout — related to necking and line-end shortening errors. “If you have on top of that also CD errors caused by dose errors between the two exposure steps, or you have overlay errors between the two exposure steps, these effects will become more visible, will become enhanced,” Ronse said. Whether or not double patterning could truly bridge the gap between immersion and EUV is a matter of timing, Fuller said, but it certainly seems feasible. “Let's say that a 1.35 NA water-based immersion tool will do a true 45 nm half-pitch. And I think that's a reasonable assumption to make here,” he said. “If you really could extend double patterning to the limit, that would say that you could drive your half-pitch down really to the 22 nm node.” A real need for a 22 nm half-pitch is probably a good five years away, which is also about the timeframe being considered now for the introduction of EUV lithography. For flash memory devices, in particular, Kool said he is confident that double patterning can bridge the gap to EUV. The 1-D structures in flash make the splitting of the patterns more straightforward. The 2-D nature of DRAM, on the other hand, makes pattern splitting more difficult. “If you look to logic, I think for some layers you can say it's quite one-dimensional, so that seems to be very doable. And for the other, the challenge is harder to achieve,” Kool said. “So particularly for the flash, I think double patterning can bring the bridge between the water immersion and EUV. If you look to DRAM, it depends a little bit on the speed of the roadmap.” With flash being the most demanding in terms of the shrinkage roadmap (Fig. 3), Kool noted, double patterning there would be welcome. Double trouble Granted, “welcome” may be too strong of a word. Although there is much talk and excitement about double patterning these days, lithographers are not exactly running to it with open arms. “I don't think that manufacturing people are warm at all. It's still the R&D people that are warm to it,” Fuller clarified. Overlay is a key concern given that alignment between the two patterns must be extremely accurate to avoid faulty circuits. “I would say, to make it production-worthy, overlay is the main parameter,” Kool said. The lithography tools that are now becoming available have an overlay somewhere in the range of 6 nm, according to Fuller. Continuing improvements will squeeze that number further. “But there's some fairly substantial engineering improvements being made for these so-called double patterning machines that will more or less cut that number in half,” he said. “In terms of the overlay numbers, they are half or even less than what you require just for single exposure overlay requirements,” Kool said. “So in terms of relating that to CD, with double patterning, you're coming to overlay requirements, I would say, somewhere just below 10% of the CD number. ” According to Franklin Kalk, chief technology officer at Toppan Photomasks Inc. (Round Rock, Texas), overlay is particularly tight for double patterning in memory and microprocessor devices — somewhere between 1.5 and 3 nm, depending on the feature. That's right in the range of what the metrology tools can measure today, he also noted. “So the metrology hurdle is also very large.” Some people have even talked about needing to get overlay accuracy down to 1 nm, but that depends on who you talk to and how the calculations are done, Fuller said. The nominal target likely to be thrown around at the Advanced Lithography conference this month in San Jose is 3 nm for overlay, which Fuller sees as possible in the next round of tools. Needless to say, 1 nm would prove more difficult. “Cutting something in half is one thing; cutting something to 20% of what we have today is a little tougher,” Fuller said. Another important factor in double patterning is the throughput hit taken by having to complete two lithography processes rather than just one. Granted, these steps will likely be taken with only the most critical device layers, but the throughput hit is nonetheless one that chipmakers do not take lightly. Double expose, single etch An alternative that would require less processing and therefore less of a throughput hit is usually called double exposure — in which the two halves of the pattern are exposed separately, but only one etch step is required, as with today's single exposure lithography (Fig. 4). “It presupposes that there is a materials solution that will allow you to do two exposures to the same material,” said Bryan Rice, an Intel assignee to Sematech (Austin, Texas), where he is immersion lithography program manager. Several potential solutions are being explored, but no final material solutions are available at this time, Rice noted, adding that Sematech is supporting the development of a number of them. “And if those materials can be developed, then they represent another opportunity for extending immersion lithography.” “I have to say, my own personal favorite, if it can be done, is double exposure, just simply because you need a special resist and you need still two reticles and so on, but you don't need all the hard masks or the extra processing, or even a separate resist coat and develop,” Fuller said. “So from a productivity and overall cost standpoint, something of a double exposure type process would be best.” However, at this point, there are not any solid candidates for the non-linear resist or contrast enhancement layer that would be necessary, Fuller said. “If something like that could be made to work, it would be very interesting, but of course it has to be compatible with immersion and so on and so on, to make it all practical.” Mask effects There have also been some concerns expressed about the already high mask costs growing further because of the doubling of the number of masks needed. But while inspection and material costs will grow, the total write time should be about the same with double patterning, thereby making writing costs about the same, according to Toppan Photomasks' Kalk. For advanced mask manufacturing today, the main cost driver is yield. That's not expected to change with double patterning, but what might change is what that yield will look like. “Today, defectivity drives the yield. It isn't placement, it isn't CD, it's defects,” Kalk said. “If you look at DRAM, which is very tight pitch, compared to MPU, where pitch isn't nearly as small, the defectivity drives us more on DRAM than it does on MPU.” Double patterning may change that (Table). “Placement and CD will become bigger yield detractors because the specs get tighter,” Kalk said, explaining that defectivity, with the relaxed pitch, will actually get easier. “I don't know if they'll be bigger yield detractors than defectivity. But certainly they'll become much more significant than they would be otherwise.” Double patterning tools “One of the things I never hear mentioned, but personally I think it's equally important to the throughput and overlay issues of double patterning, is you need to have exceptionally good image quality,” Fuller said. “An example I use is, suppose that today you're patterning with dry ArF, 70 nm lines and spaces, 140 nm pitch. And in the future you want to do 70 nm pitch, 35 nm lines and spaces. Well, by using a double pattern, you'd say, okay, I'll do my 35 nm lines but on a 140 nm pitch, just like I was doing before. But what people tend to forget is we're not interested in the 70 nm lines anymore; we want 35 nm lines. And that means that the CD control has to be better, the line edge roughness has to be better, and so it's not simply a matter of ameliorating the throughput hit for cost purposes and also the overlay, which we know would lead to some CD errors and so on. But in fact the imaging has to continue to improve as well. So it's really important to continue to drive aberrations lower and lower, and to really have a very good imaging quality and stability and all that as well on so-called double patterning tools.” Although Nikon has not yet announced anything specific, the company is certainly working on lithography tools that will better facilitate double patterning. “Of course, people haven't really assimilated 45 nm yet with high-index water-based immersion, but there are definitely tools in the works that will have much better overlay, better throughput and so on to ease some of the challenges that people are talking about,” Fuller said. At SEMICON Japan in December, ASML announced its Twinscan XT:1450, a dry ArF tool with improved imaging, overlay and throughput. ASML has positioned the tool as suitable for double patterning applications, particularly for R&D, according to Kool. Triple patterning? “There's been a little bit of talk about using more than two patterns. You could actually do, instead of a double process, a triple process,” Fuller said. However, triple patterning would create even further tolerance issues. “I think most people will have their plates full with the double exposure for the next few years.” http://tinyurl.com/5dkcel --

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