EDA still software-challenged Anne-Francoise Pele EE Times Europe (06/12/2008 1:58 H EDT) ANAHEIM, Calif. — For the third consecutive year, Gary Smith, founder and chief analyst for Gary Smith EDA, emphasized at the Design Automation Conference (DAC) that embedded software development is the biggest challenge in system-on-chip (SoC) design. Last year at the 44th DAC, Smith explained that chipmakers want EDA vendors to provide tools for all the emerging design challenges, and the most important design problem will be embedded software. His talk was then entitled: "[EDA] Alive and well but software challenged." Smith added that parallel processing was a big challenge for EDA vendors. Without the use of parallel processing, most EDA tools cannot handle designs with new semiconductor processing technologies. At the 65-nm and 45-nm nodes, many tools have to be re-written, and much existing code has to be fully replaced. At a panel session on "Trends and What's Hot at DAC" this week, Smith emphasized "software, software, software" as he said "it is the biggest problem we have got." In a commentary, Smith said: "Last year, software costs exceeded hardware costs. The Moore's law is going off the track. By 2012, we are in big trouble. And, if we go on like this, in 2015, it will cost $0.5 billion to develop a SoC." Simon Davidmann, president and CEO of Imperas Ltd., a young company developing multiprocessing development tools (Thame, England), explained to EE Times Europe that, in the last few years, several chip companies have managed to build silicon that works, but have not managed to program the devices and, ultimately, the companies have failed. Davidmann commented: "EDA has spent the last two decades solving the problem of a manageable and predictable methodology to develop chips, and it has done well. As more and more products are defined by the software that runs on these chips, the EDA industry needs to move onward and upward and encompass software development as part electronic product and system design." EDA, being historically focused on hardware, has developed some tools for hardware/software co-design or co-verification, but almost nothing focused on application software or operating systems, Davidmann continued. "Those that offer that support are the ESL tools, but still they focus on hardware and the design of the hardware —using C. The situation is changing with the introduction of some new companies, such as Imperas, building tools specifically for software development —using the experience and successes in EDA hardware but geared to software development." In March 2008, Imperas launched Open Virtual Platforms, a common, open standard solution for developers to quickly and inexpensively simulate embedded software on SoC designs. OVP includes APIs, open source models and a free simulator to help software teams to develop their code. Davidmann's last words were that the situation has evolved, but more on the user side than on the EDA side. He declared: "Software teams of today are starting to realize that they cannot get software to work on chips without using virtual platform simulation. This realization has motivated the move to using simulation as a platform for software development; this has become essential for multicore embedded software. According to Dr. Luc Burgun, president and CEO of Emulation and Verification Engineering (EVE) SA, there is a huge challenge for software developers to exploit the potential computing power offered by multicore architectures. Also, Burgun stressed that, "multicore will also generate tremendous challenges for hardware designers since it is an opportunity to design much bigger chips. These challenges will escalate the pressure on verification — including hardware-software integration —, back-end implementation and manufacturing." http://www.eetimes.com/news/design/showArticle.jhtml?articleID=208403665 -- ◣ ◢ .. ◥S --

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