Addressing manufacturing variation at advanced nodes with silicon-contour-based DFM (圖文): http://tinyurl.com/2pvlxw Solid State Technology March, 2008 Author(s) : Nitin Deo Applying foundries’ recommended design rules can often raise design costs because many recommended design rules result in trade-offs, requiring designers to spend more time in verification. In addition, as these rules are applied to every structure in the design, it often results in bigger die size. A silicon-aware design methodology can be used to evaluate intelligent design trade-offs and identify potential failures due to systematic manufacturing defects during the design phase. Applying a silicon-coutour-based method will be increasingly important as designers move into 45nm designs and beyond. The set of design for manufacturing (DFM) recommended rules provided by foundries to designers is primarily litho-driven, but cannot guarantee a manufacturable design without overly restrictive design requirements. The rule-based methodology of making design decisions based on idealized polygons no longer represents what is actually on the silicon and needs to be replaced. Conversely, model-based hotspot detection and silicon-aware parametric analysis help designers optimize chips for yield, area and performance without the burdensome cost of applying foundries’ recommended design rules. Using model-based simulation of the lithography, OPC, RET, and etch effects, followed by electrical evaluation of the resulting shapes, leads to a more realistic and accurate analysis. DFM methodology We are currently at a point of inflection where designers need more predictability in design to offset the variations induced by manufacturing processes such as lithography and etch. At 90nm and below, perfect squares and rectangles from GDSII patterns are converted into contours on silicon. Unfortunately, regardless of how many OPC/RET techniques are applied to those ideal shapes, they turn into contours and thus change the characteristics of the active and passive layers of the chip. This variability then gets worse across process window. Since the design implementation and analysis is based on ideal GDSII shapes, there are substantial differences between the design stage and actual wafer. The variation in performance increases with shrinking geometries. A successful DFM design methodology consists of three parts: 1) achieving a more aggressive layout through limited usage of litho-related recommended design rules; 2) identifying and fixing hotspots; 3) improving tuning accuracy. By following the steps outlined below, designers will be able to better predict the outcome of their designs in silicon: Aggressive layout. A 10-15% density improvement is achieved by using more aggressive design rules. DFM/recommended-provided by the foundry-design rules are used only if there is no impact on cell size. Identifying and fixing hotspots. By using a model-based layout printability checker, model-based litho and etch simulation are done at the cell level to identify hotspots. Violations of recommended rules may cause additional hotspots, which are then fixed. Improving analysis accuracy. Using a process-aware parametric analysis tool for transistors and interconnect using contours of diffusion, poly and metal layers for parametric analysis, improves analysis accuracy as it brings silicon accuracy into the design stage. As IC designers work on 45nm chips in the ideal world of GDSII, in which squares and rectangles are used without any regard to the silicon reality in X, Y, or Z directions, they are realizing that even though their designs may be fully DRC-clean and timing-clean, they are not getting the entitled yield or entitled performance (timing and power) from their designs. Furthermore, manufacturers are realizing that there is a significant pattern dependency on manufacturing variability. Figure 1. Increasing complexities of nanometer technologies. Two different designs that are fully DRC-clean are showing very different physical and electrical characteristics after manufacturing. The main reasons for this discrepancy are depicted in Fig. 1. Via reliability, prevention of opens and shorts due to random particle defects, systematic manufacturing issues such as lithography-driven physical and electrical variations, and finally, random process variations causing timing and power variation, are the main causes of failures or underutilization of the process. Variability: A fact of life at 45nm Designers design with ideally drawn GDSII shapes like squares and rectangles for various structures to implement functionality. However, when these structures are printed on silicon, they turn into rounded shapes, i.e. contours. These contours bring variation in the physical structures that could cause complete breakdown, leading to yield loss. But even if that extreme doesn’t happen, it leads to electrical variation (timing and power) that might lead to functional failure of chips. Guardbanding the timing and power parameters, i.e. adding a global margin, is not sufficient to address such variability. The fact that this variability can be spread around the assumed characteristics of active devices and passive components makes it harder to mask these electrical failures with a simple addition of margins. Besides, adding a margin of 15-20% to timing leads to underutilization of the advanced process technologies. Rule-based systems cannot cover the complex relationship among layout structures, electrical requirements of a design, and process conditions. This complex interdependent relationship can only be modeled and has to be made available to designers in ways to which they are accustomed, i.e. with utmost usability and run-time, as well as predictable closure between analysis and correction. Silicon-contour prediction during design The consequences of ignoring variability are unpredictability, lower yield, and lower performance. The way to bring back the predictability into a design and optimize for yield and performance is to deal with the variability by bringing silicon contours into the design stage and then analyzing the design for catastrophic and parametric failures. This is the foundation of a true ‘ design’ for manufacturing methodology. At 65nm, device sizes are well below the wavelength of light used to pattern them, and 2D shape effects begin to impact transistor characteristics. Shape effects for poly gates and diffusion must be accounted for at design time during circuit simulation. Since diffusion geometries can be within 2× of gate length, it is important to include narrow width effects when calculating currents of these transistors. These narrow width effects are due to STI edge geometry, stress, and non-uniform dopant distributions along the width of the channel. These effects can have a significant impact on device currents, with drive currents differing by up to 30% and off currents by over 2×. Using an accurate model of the current density through the device width, and detailed knowledge of the device shape, currents for 2D transistor shapes can be predicted with close correlation to actual silicon measurements. Figure 2. The compact model on the right encapsulates the entire maskmaking flow on the left, to predict silicon contours from drawn layout. Device shapes can be predicted using a compact model encapsulating the maskmaking flow. Unlike a traditional lithography simulation model that only captures the behavior of the lithography system, this compact model encapsulates the entire manufacturing process, including the retargeting, assist-feature, PSM, OPC and lithography effects as shown in Fig. 2. Using such a compact model at different process points (focus, exposure), the silicon contours of poly gate layer can be predicted. Using the model for the active layer, contours can be derived for the diffusion layer also. This systematic shape variation on silicon can lead to changes in the drawn current of a transistor that must be predicted for accurate circuit simulation. Figure 3. Model-based design manufacturability checking (DMC). A model-based design manufacturability checker (DMC) (Fig. 3)-also known as a layout printability checker-detects manufacturability issues missed by traditional DRC checks in a fraction of the time required by other proposed solutions based on OPC and lithography simulation. It allows designers to improve yield during physical design implementation by quickly and accurately accounting for systematic manufacturing variations. Electrical DFM Transistor performance depends heavily on the shape and dimension of polysilicon gate and diffusion. A small gate variation changes the channel length, creating a variation in Ion and Ioff. Dependence of transistor current is increasingly nonlinear in channel length. As a result, the variability in current Ion and Ioff has been increasing with process node size, as shown in Fig. 4. Figure 4. Ion and Ioff variation due to change in channel length. A 10% transistor gate variation can translate to as much as -15% to +25% gate delay variation, as shown in Fig. 4a. Even worse variations are seen on Ioff in Fig. 4b. The impact of variability is reported to cause 6% of CD variations that produces enough leakage to create an IDDQ chip failure. Even small shape variations of diffusion and poly layers can translate into large nonlinear performance variation. Since the lithography-induced variations have a direct impact on timing, power, and noise, one could ask the question: are existing solutions adequate for sub-90nm designs? Today’s timing verification techniques use “corner case” analysis to estimate the device electrical characteristics on timing. These corner models are derived from idealized test structures on silicon that do not reflect possible systematic shape variations due to layout context. The ±3 sigma “corners” derived from measurements sampled on multiple die and wafers have to be further guard-banded to attempt to account for the effects of systematic variations. Guard-bands do not prevent undetected noise failure, and accurate device behavior prediction is essential for capturing all possible noise failures. Today’s guard-bands in interconnect extraction are typically -20% to +30%. At 65nm, the layout parasitic extraction approach used in existing extraction methodologies is inadequate to predict the systematic variations in device and interconnect delays dominated by shape variations. Conclusion Sub-90nm design requires the modeling, characterization, and prediction of true sub-90nm effects on timing, power, and signal integrity. The increasing dependence of overall chip performance on shape, due to the nonlinear behavior of both interconnect and transistors, requires accurate prediction of systematic shape variations for optimizing and control of the impact of lithography, mask, etch, RET, OPC, and CMP effects on their chip parameters. There are three major benefits of this silicon-contour based methodology with regards to both physical and electrical DFM: Designers can improve parametric yield and chip performance by accurately determining the impact of systematic variations during design. Designers can quickly achieve the desired predictability. Designers can reduce sensitivity to manufacturing variations and performance spread. Using a comprehensive DFM methodology reduces the parametric yield loss and leads to maximized utilization of the process. Nitin Deo received his BSEE from Mysore U., his MSEE from Virginia Tech, and his MBA from San Jose State U., and is group director of DFM marketing at Cadence Design Systems, 2655 Seely Ave., San Jose, CA 95134 USA; ph 408/944-7584, e-mail [email protected]. --

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