作者yellowfishie (喵喵喵喵~~~)
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標題[研究] Double-patterning may bail out industry
時間Sun Mar 2 15:48:58 2008
Double-patterning may bail out industry
Mark LaPedus
(02/23/2006 9:21 H EST)
URL:
http://www.eetimes.com/showArticle.jhtml?articleID=180207176
SAN JOSE, Calif. — Immersion lithography could be late to the market,
forcing chip makers to consider 193-nm “dry” and double-exposure techniques
for chip production at the 45-nm node and beyond, according to South Korean
memory giants Hynix Semiconductor Inc. and Samsung Electronics Co. Ltd.
Many chip makers are scrambling to get 193-nm immersion lithography in
production for the 45-nm node in the 2007 time frame. But in separate papers
at the SPIE Microlithography conference here this week, Hynix and Samsung
indicated that 193-nm immersion is still behind for insertion in the
development of NAND-based flash memory devices at the 50-nm node.
The lack of immersion lithography will make 193-nm “dry” and
double-patterning techniques “unavoidable,” according to a paper from Hynix
at SPIE. With 193-nm double-patterning, Hynix claims to have developed a
50-nm, half-pitch NAND device with good CD uniformity.
In another paper, Samsung believes that double-exposure is better suited for
flash and DRAM manufacturing, as compared to logic production. “Indeed,
immersion is not fully ready,” according to a paper from Samsung. “
Double-exposure is becoming a stronger candidate as throughput issues are
getting better.”
Double-exposure is an expensive technology that has been debated for years.
In this technique, to be done with 193-nm “dry” scanners, “each
lithography step is completed by a combination of two separate resist and
etch steps; hence, the physical limit of resolution, 0.25 k1, can be overcome
with in a double-patterning scheme,” according to the Hynix paper.
In one presentation, IMEC surprised an audience at SPIE when it noted that
193-nm immersion with double-exposure techniques represents the “lowest risk
to the 32-nm half-pitch node.” Extreme ultraviolet (EUV) and 193-nm
immersion are also candidates for the 32-nm node, according to IMEC.
Double-patterning is an insurance policy for the semiconductor industry — if
the other solutions do not work, said Farhad Moghadam, senior vice president
and general manager of the Thin Films product business group at Applied
Materials Inc. (Santa Clara, Calif.).
But besides the costs, there are some overlay issues associated with
double-patterning, Moghadam said. At 45-nm, chip makers may end up inserting
193-nm “dry” with double-exposure instead of immersion, which could miss
the market window, he said.
“Immersion will eventually happen,” he said, but “it’s very unlikely”
that chip makers will insert the technology at the 45-nm node.
Still, others are moving full speed ahead with immersion despite the current
and nagging defect issues with the fledging technology.
Silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) said
that immersion lithography is “nearly production ready.” TSMC claimed that
its immersion lithography program has produced test wafers well within
acceptable parameters for volume manufacturing. TSMC's immersion lithography
technology is targeted for its 45-nm manufacturing process, which is slated
for 2007 or so.
Chartered, IBM, Infineon, TI and others are also banking on immersion for
45-nm. And the tool makers themselves claim that they are on track with the
systems.
After shipping its first hyper NA tool, Japan’s Nikon Corp. disclosed the
details of its next-generation immersion lithography tool for use in chip
making down to the 32-nm node. Nikon’s new scanner, dubbed the NSR-S610C, is
a 193-nm immersion tool with an NA of 1.30.
Defects are not an issue with Nikon’s immersion scanners, said Soichi Owa,
Nikon Fellow and development manager for Nikon (Tokyo), in a presentation
SPIE.
The S610C system is geared for memory production down to the 45-nm half-pitch
node and logic chip manufacturing at 32-nm, said Bernie Wood, director of
marketing at Nikon Precision Inc. (Belmont, Calif.). Shipments are due by year
’s end.
Nikon’s rival, ASML Holding NV, will shortly ship its first hyper NA tool,
the Twinscan XT:1700i, a machine geared for the 45-nm node. “We’re on track,
” said Peter Jenkins, vice president of marketing for ASML (Veldhoven, the
Netherlands). “It’s the only machine in the market that can support 45-nm.”
That system is made using a combination of a 1.2 NA catadioptric lens,
polarized illumination and water based immersion technology. ASML expects to
ship between 20 and 25 Twinscan XT:1700i immersion lithography systems in
2006.
And not to be outdone, Canon Inc. is expected to ship a 193-nm immersion tool
with an NA of 1.30 by the end of this year or early next year.
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