Needed: A new design-to-fab flow for advanced ICs Jean Marie Brunet & Sudhakar Jilla EE Times (11/13/2007 10:12 H EST) Several trends are aligning to make the physical design and verification flow much more challenging than ever before. We are pushing well beyond the traditional limits of visible light lithography. As geometries shrink, the performance of devices and interconnects becomes much more sensitive to small variations in the rendered shapes. Also, it has become common for new designs to begin to use multiple operational modes. Sections of a particular device might be powered down at times to conserve energy, thus ensuring that the device does not have to run at different combinations of supply voltage and clock frequencies. These considerations are being added to the traditional environmental variations, such as ambient temperature and voltage supply tolerances, resulting in a need to perform physical design analysis and optimization for many modes and corners at the same time. With design rules becoming so numerous, complex and subtle, the sign-off decision itself is evolving from a relatively straightforward pass/fail proposition to an assessment of manufacturability and expected yield based on probability distributions. Tools are breaking, tapeouts are taking longer, and yield ramps are becoming slower. These new challenges begin to appear around 90nm and become progressively worse with each successive node. Depending on the specific design and process, these issues can become critical at 65nm; and the majority of 45nm designs will require more advanced methods and tools to achieve rapid tapeout with high confidence in manufacturability and parametric yield. At 45nm the router may be unable to converge on an optimum layout at all, no matter how long it works! This is what we observe in practice: at advanced nodes, the traditional routing algorithms are becoming the tapeout bottleneck, and closure is extending from days to weeks or even months. The tools are choking, and designers are left to attempt hand-optimization for advanced design rule checking (DRC) and design for manufacturing (DFM) improvements, or simply to take the risk of tapeout and hope the design will be manufacturable. To transit this bottleneck, electronic design automation (EDA) tools for nanometer ICs have to incorporate advanced DRC and DFM checks as early as possible in the place and route process, beginning at the global routing stage. In addition to the complex DRCs, the tool also needs to consider the litho, the critical area analysis (CAA), and other DFM models during place and route to prevent layouts that negatively affect DFM scores. The prescription sounds logical and straightforward, but the implications for the tool architecture are profound. For one thing, it means that the P&R tools need a built-in DRC checker that operates on complete polygons--not just edge-to-edge measurements--and is extremely fast, comprehensive, accurate, and incremental. In the past, design rules were expressed as relatively simple linear measurements with a fixed threshold, such as the minimum distance between adjacent interconnect wires. At advanced nodes, design rules are multi-variable equations expressing complex spatial constraints and relationships between design features within a certain 3D proximity. Because the design rules are more numerous and more complex, the computational complexity of design rule checking and the number of potential violations have both grown exponentially. As we noted earlier, the first step in dealing with this new reality is to avoid as many violations as possible at the place and route stage. Nevertheless, some violations will be impossible to avoid at the physical verification (PV) signoff stage. There are two implications for EDA tools at this stage. First, we need to accelerate the total cycle time for locating and removing the remaining violations. This acceleration can be accomplished by assuring the fastest possible DRC run time using techniques such as improved data structuring, hierarchical processing, more efficient memory usage, multithreading and distributed computing. Multithreading is particularly important today because volume microprocessor companies, such as Intel and AMD, have turned to multicore architectures to deal with runaway heat density in their products. In the future, all EDA tools will need to exploit a high degree of processor parallelism to extract the maximum amount of computing power from off-the-shelf platforms. Another way to reduce total turnaround time is to shift from a sequential to a concurrent work-flow model. In this approach to design rule repair, the PV tool provides an immediate view of violations as they are discovered in a DRC run, along with visual aids to help the designer quickly locate and repair the source of the violations. After making a repair, the designer can immediately initiate a parallel DRC run to ensure that the fix has not caused any new problems. In this manner, the designer can work efficiently without waiting for complete DRC execution. In addition, early feedback on fixes means that side effects from fixes, which can ripple through designs causing new violations, are minimized. The tools also support the designer in this process by keeping track of which violations have been repaired, resubmitted, and verified, as well as by providing the ability to focus verification on specific areas of the design or on only the changes made since the previous run. Hard and soft rules The second impact to PV tools is that design rules must now be viewed as a spectrum ranging from the traditional "hard" rules, whose violations must be removed before tapeout, to "soft" or recommended rules that improve the manufacturability, and hence expected yield, of designs, but are not required by the foundry. There tend to be many more recommended design rule (RDR) violations than hard DRC violations during signoff, and the challenge facing the designer is to decide which of the RDRs should be followed and which of the violations should be repaired. Of course, this is a trade-off between time-to-market and manufacturing yield. But what are the decision criteria? To address this question, PV flows for advanced nodes incorporate DFM tools that can assess the design by providing a "DFM score" giving the designer a gauge of manufacturability. Over time, DFM scores can be correlated to actual manufacturing yield to help close the loop between design and manufacturing output, a process often referred to as "improvability." DFM tools also provide a view of RDR violations and DFM suggestions as a graded set of "improvability options." Like a Pareto chart, the DFM grading tells the designer which actions will have the most effect on yield. As in most quality improvement disciplines, the 80/20 rule can be applied to maximize the benefit of improvability efforts. As we move to 45nm and beyond, post-tapeout processing becomes even more critical, because we are pushing lithography well beyond previously expected limits. Critical dimensions are now about a quarter of the exposure light wavelength, so extensive optical corrections are needed to make the lithographic process work. OPC software must be more accurate than ever before and also have a greater capacity for holding huge amounts of data. Obviously, the computational load is tremendous, and the tapeout-to-mask flow threatens to become a major bottleneck in achieving rapid time-to-market. Two advances that have enabled OPC to keep up with the demands include a greater density of modeling and coprocessor acceleration (CPA). Dense modeling evaluates the layout geometry on a high-resolution grid. By optimizing OPC software for mass-produced CPA platforms, suppliers can deliver high accuracy and performance at a relatively low cost compared to custom hardware. As we move toward 32nm and 22nm, additional techniques will be required, such as double patterning. This technique will create new processing steps and will most likely introduce new design constraints that will be reflected in the DFM and DRC tool flows. http://www.eetimes.com/news/design/showArticle.jhtml?articleID=202805759 --

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