Routing experts launch 'interconnect synthesis' startup Richard Goering EE Times (05/23/2007 11:37 H EDT) The founders of startup Nanovata Design Automation helped develop some of the best-known IC layout products in the world, including Apollo, Astro and Columbia from Avanti Corp. Now they've banded together to provide "interconnect synthesis" technology that optimizes IC layouts for timing, signal integrity, yield and manufacturability. Nanovata is making its first public appearance at the upcoming Design Automation Conference, but doesn't plan a product announcement until the third quarter. The company's plan is to offer shape-based routing technology that can improve signal integrity, install "yield enhancing" vias, and optimize critical areas. "We produce interconnect synthesis tools to improve performance and optimize yield," said J.T. Li, Nanovata CEO and founder. "We position ourselves as an optimization tool complimentary to existing routing solutions." After working for AT&T Bell Labs, AMD, and PiE Design Systems, Li joined Avanti, then called ArcSys, in 1995. He led the effort to develop the Apollo routing product, and then left Avanti in 2000 to join Nassda as vice president of digital product development. He left Nassda after Synopsys bought the company in 2005. Another founder, Chih-Liang Cheng, was a developer for Apollo and Astro. A third founder, Chung-Do Yang, worked on the Milkyway database and the Columbia chip assembly router. A fourth founder, Hsi-Chuan Chen, was briefly at Avanti and then helped develop First Encounter at Silicon Perspective Corp. (SPC) before its acquisition by Cadence Design Systems. Nanovata now has 8 employees and has raised around $2 million in funding, Li said. The company started beta evaluations last year and has gone through production on five chips. Nanovata's first product will be a "plug and play" interconnect optimization tool, Li said. It will aim to improve chip timing and yield, and make layouts more amenable to optical proximity correction (OPC), by using a shape-based routing approach to shift wires. Without changing the netlist and placement, Li said, Nanovata's technology can optimize interconnect in order to reduce capacitive loading and resolve signal integrity problems. "We can find out which net has a severe signal integrity impact, and we can increase the spacing around critical nets and reduce signal integrity," he said. The Nanovata technology can also install "yield enhancing" vias, he said. This may include redundant vias, but sometimes that's prohibitive from a timing standpoint. In such cases the tool can make the metal enclosure of the via larger in order to improve yields. Nanovata can provide up to 95 percent yield enhancing vias without sacrificing timing, Li said. Nanovata's tool will also help reduce critical areas by adding more space around critical nets. It does this through wire spreading. Because the technology is shape-based, Li said, it has a much larger "solution space" than a gridded approach would have. It also claims to be fast. On a 7.8 mm by 7.8 mm chip with 1.9 million placeable instances, he said, Nanovata was able to output an optimized DEF layout file in one and a half hours. Large EDA vendors may try to add similar technology, but Nanovata has an edge, Li said. "The reason we can stay ahead is our shape-based technology. Our optimization is much finer, and our impact for yield is much better, than grid based technology." http://tinyurl.com/26zgvp --

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