Folks, Now you can download global routing contest benchmarks from: http://www.ispd.cc/rcontest/[benchmark_name] adaptec1.capo70.2d.35.50.70.gr.gz adaptec1.capo70.3d.35.50.70.gr.gz adaptec2.mpl60.2d.35.50.70.gr.gz adaptec2.mpl60.3d.35.50.70.gr.gz adaptec3.dragon70.2d.30.50.70.gr.gz adaptec3.dragon70.3d.30.50.70.gr.gz adaptec4.aplace60.2d.30.50.70.gr.gz adaptec4.aplace60.3d.30.50.70.gr.gz adaptec5.mfar50.2d.25.50.70.gr.gz adaptec5.mfar50.3d.25.50.70.gr.gz newblue1.ntup50.2d.30.50.70.gr.gz newblue1.ntup50.3d.30.50.70.gr.gz newblue2.fastplace90.2d.50.50.70.gr.gz newblue2.fastplace90.3d.50.50.70.gr.gz newblue3.kraftwerk80.2d.40.50.70.gr.gz newblue3.kraftwerk80.3d.40.50.70.gr.gz There are 8 benchmarks, 4 from ISPD 05 benchmark and another 4 from ISPD 06 benchmark. I intentionally didn't put these in global routing contest website yet. I'd like to ask you guys to run these first, just make sure benchmarks are valid. Once every thing seems to work, then I'll create links to these at the official website, probably next week. There are a few things I'd like to point out. Please read this email carefully, and if you have any question or concern, let me know as soon as possible. 1. For all circuits, there are 6 metal layers, from M1 to M6. Note that there is no M0 metal layer. Every pin is located in M1. M1, M3 M5 are designated for horizontal wires while M2, M4 M6 are used for vertical wires. This means that vertical capacities in M1, M3 and M5 are 0. Similarly, horizontal capacities in M2, M4 and M6 are 0. 2. In real designs, it's very hard to use M1 & M2 for signal routing because those layers are heavily used for cell internal routings. To reflect this, you'll see that the capacities of M1 & M2 are about 20% of normal capacities of other metal layers. 3. In all benchmarks, now you'll see "capacity adjustment" section. Please note that this section was NOT included in sample benchmarks. Your router has to honor these constraints. The format goes like the following: 254372 /* Total number of adjustment */ 409 438 3 410 438 3 10 /* the capacity of edge (409,438)->(410,438) in M3 is 10 */ 82 504 3 83 504 3 10 226 177 3 227 177 3 10 ...... Please note that new capacity (in this example, 10) OVERWRITEs normal capacity specification in header section. These capacity adjustments were derived from the locations of big macros in placed solutions. When there are big macros, significant wiring resources are consumed by these macros leaving less wiring resources for other signal routings. The capacity adjustment section reflects that effect. In reality, the actual capacity adjustments should be different from block to block. But in our benchmarks, most of them have similar values. It is possible that some capacity becomes 0. This implies that the tile spans over more than one macro blocks. Also, there are trivial capacity adjustments that are not specified in this section. I.e., vertical capacity of M1/M3/M5 and horizontal capacity of M2/M4/M6 are all 0. 4. In real life, you can route a net with different width/spacing, and each metal layer has different minimum width and spacing. To simplify the process, however, for our global routing contest, we'll just assume that every net is routed with minimum width and spacing. I intentionally set the minimum width and spacing to 1 for all layers. As specified in website already, when you calculate the usage of wires, you need to consider (width + space) instead of width alone. For example, if the capacity of an edge is 10, then you can route 5 nets through that edge assuming minimum width and space are 1. For another simplicity, I set the via width and spacing to 1 also. As you know, different metal layer has different size of vias and spacing rules. But for our contest, let's stick to 1 for both via width and area. 5. For each benchmark, you'll see 2d and 3d version. Essentially, they represent the same problem. The only difference is that 3d version has 6 metal layers while 2d version has only 2. The horizontal (vertical) capacity of 2d version is set to the sum of horizontal (vertical) capacities of all horizontal (vertical) metal layers or little less than that. But the difference is not that much. 6. The solution output file of these benchmarks will be huge. So, please do NOT print your solution tile by tile. In other words, if your net segment goes through (5, 5)->(5, 6)->(5,7)->(5,8) tiles, your solution should be a single line: (5, 5, layer)-(5, 8, layer), not 3 lines. 7. In sample benchmarks, 1 pin nets were included inadvertently. In contest benchmarks, you shouldn't see any 1 pin nets. If you find one, let me know. Also, you don't have to route a net with more than 1000 pins. For those nets, you don't have to dump out any solution. Also, some nets will be contained in a single tile. Those also don't have to be routed. You'll see about 10-20% of nets are contained in a single tile. 8. If a net changes metal layers (i.e., via-via connection), you add 3 wire length units to your wire length calculation. In other words, via-to-via connections are sort of embedded into your wire length calculation. Whenever you're using vias, it will increase your routed wire length. 9. To judge the quality of your solutions, we'll consider 3 factors, total wire length, max/total overflow, and total number of vias. Here is how we measure the quality of your solutions. We'll classify your solutions into 2 groups. Group 1 contains solutions without any overflow while group 2 solutions have some overflow. The best solution of group 2 CANNOT beat the worst solution of group 1. Therefore do your best to route all nets without any overflow. In group 1, wire lengths will determine the quality of your solutions. If there is any tie, the number of vias will be used as a tie-breaker. For group 2, the following modified wire length calculation will be used: TWL = 0; for each net if a net doesn't have an overflow edge WL = routed net WL else break a net into a set of horizontal/vertical segments WL = sum { max_overflow_of_segment(i) * segment_length(i) } TWL += WL This function determines the wire length penalty when a net has any overflow edge. The magnitude of penalty will grow as a net passes through congested area. Although CPU time is not a factor for measure this time, it's always a good idea to make your tool efficient. We *might* have a on-site (separate) contest during ISPD to pick the best router that can route a few circuits successfully with the least amounts of routing resources. For this matter, we need to run lots of global routers during a short period time, and we have to limit your CPU time usage. Thus, the faster your router is, the better it will be. 9. We're working on a solution checking/evaluation script right now. I'm expecting you'll get one sometime next week. The exactly same script will be used for measuring quality of your solutions. 10. You may tune your router per circuit. But you need to send me exact parms you used so that I can reproduce your solutions. 11. The release of benchmarks is delayed. So I'm allowing a few more days for the submission of your binary and solutions. Please send me those by March 12th (Monday) noon in US central time. This gives me about 5 days for me to verify your solutions. Please send me a linux binary with statically linked libraries. If you want, you can send me a testing version to make sure your compilation method works. That's all. Let me know if you have any questions. Usually, I respond to contest related questions once in a day, but it's very possible that I miss a few occasinally. So, if you don't hear from me in a day, feel free to bug me with another emails. Gi-Joon --

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