http://www.eet.com/news/latest/showArticle.jhtml?articleID=193105393 Synopsys automates die size optimization Richard Goering EE Times (10/09/2006 9:01 H EDT) SANTA CRUZ, Calif. — In many consumer applications, a smaller IC die size can mean the difference between profitability and loss. Such apps are the target for a new Synopsys Inc. technology, called MinChip, that claims to find the smallest routable die size automatically. Rather than roll MinChip as a separate product or option, Synopsys will integrate it into the JupiterXT floor planner by the end of this year, said Bernie Mortell, product-marketing manager for Galaxy implementation tools. And since all of Synopsys' floor-planning capabilities are being integrated into IC Compiler, she said, MinChip will be available to IC Compiler users as well. MinChip takes in a floor plan after trial routing and placement. It runs what Mortell called a "virtual placement and virtual routing" until it finds the smallest possible die size. Users still must perform final routing and optimization, and run design closure for timing, power and signal integrity. "I think all customers can take advantage of this, but the customers who will have the most value are people designing high-volume parts for consumer electronics," Mortell said. Today, she noted, finding the smallest routable die size is a manual process that lacks predictability and can require many iterations. MinChip, she said, will "take your current netlist, shrink it to the smallest size and do it in one pass. You don't have to go through multiple iterative loops." The automated approach reduces the drain on engineering time and resources, she added. MinChip appears in JupiterXT as an extra command. While MinChip changes the placement, it preserves the "relative placement" of the design, Mortell said. It thus preserves the macro placement, pin locations, and chip or block shape. Users can run MinChip automatically, Mortell said, or they can give it some guidance. For instance, users can ask it to keep embedded components in a fixed location, preserve spacing between blocks or focus on a section of the die. The technology claims run-times of about four hours for 2 million gates or one hour for 400,000 gates. Synopsys says MinChip achieved average area reductions of 9 percent on internal testing with customer designs. Some of those designs, Mortell noted, had already been manually optimized for die size reduction. Some that weren't saw reductions as high as 36 percent. MinChip won't appreciably affect other design parameters, Mortell said. "In general, we've observed that timing doesn't change that much. We think that when you can achieve a smaller die area, that helps with yield. And you may see better power performance in terms of voltage drop, because everything is closer together." Best of all, perhaps, users don't have to buy anything extra. "We believe this adds fundamental value we can provide to our customers," Mortell said. MinChip is in limited customer availability now. --

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