作者yellowfishie (喵喵喵喵~~~)
看板NTUGIEE_EDA
標題[研究] TSMC reference flow 7.0
時間Wed Aug 23 09:28:12 2006
TSMC reference flow 7.0
+Statistical Timing Analysis
Design for Manufacturing (DFM)
Reference Flow 7.0 includes key DFM features that designers can exercise
throughout the design cycle. For example,
critical area analysis (CAA)
proactively identifies potential random manufacturing defects and drives wire
spreading and wire widening corrective actions.
Virtual chemical mechanical
polishing (VCMP) analysis identifies metal and dielectric thickness variation
hot spot, and guides dummy metal insertion to improve thickness uniformity
throughout the chip. In addition, selected lithography process check (LPC)
post-production tools have been qualified by TSMC as DFM compliant.
New Implementation Track
Reference Flow 7.0 includes a third implementation track partner,
Magma
Design Automation. Similar to the implementation tracks featuring tool sets
predominantly from Cadence and Synopsys, the new Magma track delineates a
complete methodology using mostly Magma’s tools. The flow has been validated
by TSMC and is available immediately.
http://www.tsmc.com/chinese/c_services/c01_design/c0105_reference.htm
http://tinyurl.com/jchv4
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