TSMC, UMC ready for 65-nm X Architecture designs Dylan McGrath EE Times (05/25/2006 12:13 H EDT) SAN FRANCISCO — Cadence Design Systems Inc.'s X Architecture has been validated for 65-nanometer production by the world's two largest silicon foundries, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and United Microelectronics Corp. (UMC), the companies said Thursday (May 25). Both Hsinchu, Taiwan-based companies say they are working with Cadence to engage mutual customers toward X Architecture production designs at leading process nodes. "TSMC and Cadence have engaged with multiple customers for 0.13-micron, 0.11-micron and 90-nm X Architecture production designs, and are now working with early customers targeting our 65-nm process," said Ed Wan, senior director of TSMC's design services marketing, in a statement. TSMC said it is providing 65-nm X Architecture design rules that allow customers to achieve lower cost, higher performance and lower power designs. Both companies tout history with the X Architecture, an approach for orienting a chip's interconnect wires using diagonal routes in addition to traditional right-angle "Manhattan" routing, which was introduced in 2001. Last year, TSMC became the first foundry to produce an X Architecture device, a PCI-Express graphics processor from ATI Technologies Inc. UMC was the first pure-play foundry to join the X Initiative. "UMC has been working with Cadence for several years to bring the advantages of the X Architecture to mainstream SoC designers," said Patrick Lin, chief SoC architect at UMC. "We are delighted to extend our readiness of this technology to the 65-nm generation, as leading customers can now leverage the X Architecture with the industry's most advanced process technology to increase the competitiveness of their products." Both companies say they are now production-ready for 130 nm, 90 nm and 65 nm. TSMC also offers 110-nm X Architecture capability. The X Architecture is said to provide improvements in chip area, performance, power consumption and cost by enabling designs with shorter wirelengths and fewer vias. http://tinyurl.com/l993c --

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