作者yellowfishie (喵喵喵喵~~~)
看板NTUGIEE_EDA
標題Re: paper review
時間Tue Nov 15 00:21:45 2005
※ 引述《crazying (追殺大象)》之銘言：
※ 引述《Donnie ( XD)》之銘言：
bluetai:
unisun:
athena:
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crazying: Computing Control Inputs in Open Systems using SAT
Optimal Design Of CMOS LNA using Multi Objective Genetic Algorithm
donnie: (1) A VLSI LAYOUT LEGALIZATION TECHNIQUE BASED ON A GRAPH FIXING ALGORITHM
(2) “Kreatur” A UML2SpecC Translator
gwliao:
(1) Leakage and Dynamic Power Reduction for DFT Circuits Operating
in Normal Mode
(2) Fast and Accurate Peak Power Estimation Through Mixed-Level
Delay Calibration
(3) Design of Low-Power CMOS Op-Amps Via Non-Convex Polynomial
Optimization
(4) Optimal Design Of CMOS LNA using Multi Objective Genetic
Algorithm
nextme: 1. A Partition-Based Voltage Scaling Algorithm
Using Dual Supply Voltages for Low Power Designs
2. ??????
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Jiawei: Design Migration from Peripheral ASIC Design
to Aera-IO Flip-Chip Design by Chip I/O Planning
and Legalization
waves: The Fast and Accurate Worst-Case Determination
with Maximum Probability
fish: 1. A Novel Heuristic for Constructing Hexagonal Steiner Trees for
Routing in VLSI
2. A Comparative Study of Lukes Algorithm and Modified Lukes
Algorithm for Partitioning of Trees
3. Design Migration from Peripheral ASIC Design to Aera-IO Flip-Chip
Design by Chip IO Planning and Legalization
4. Tapping Point Numerical Search for Exact Zero-Skew RLC Clock Tree
Construction
Mark:
1. A Novel Heuristic for Constructing Hexagonal Steiner Trees
for Routing in VLSI
2. Speeding Up Static Timing Analysis With Crosstalk:
Discrete Coupling Model Centric Approach
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meifc: Improving Single-Pass Redundancy Addition and Removal
internal: gain-based cell delay modeling
Tien-Chang Hsu Multilevel Large-Scale Modules Placement
with Refined Neighborhood Exchange
anna: Speeding Up Static Timing Analysis With Crosstalk:
Discrete Coupling Model Centric Approach
--------
enorm: Formal Presentation of Two Initial Variable Ordering
indark: Investigation of dynamic power consumption
reduction in FPGAs
Akilae: Automatic Low Power Optimizations during ADL-driven ASIP
Design
jinli: A Linear Time Complexity Current Path Analysis Algorithm
for ESD Protection
hyliu: Modified Simulated Annealing Algorithm for Large Temperature
Set Applications – Simulation of VLSI Floor Planning System
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※ 編輯: Donnie 來自: 140.112.25.204 (11/14 23:55)
※ 編輯: Donnie 來自: 140.112.25.204 (11/14 23:58)
※ 編輯: Donnie 來自: 140.112.25.204 (11/15 00:00)
※ 編輯: Donnie 來自: 140.112.25.204 (11/15 00:01)
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