※ 引述《Donnie ( XD)》之銘言： nextme: *. A Partition-Based Voltage Scaling Algorithm Using Dual Supply Voltages for Low Power Designs 2. Improving Single-Pass Redundancy Addition and Removal with Inconsistent Assignments 3. Gain-based Cell Delay Modeling 4. Fast and Accurate Peak Power Estimation Through Mixed-Level Delay Calibration Jiawei: Design Migration from Peripheral ASIC Design to Aera-IO Flip-Chip Design by Chip I/O Planning and Legalization waves: The Fast and Accurate Worst-Case Determination with Maximum Probability -------- meifc: Improving Single-Pass Redundancy Addition and Removal internal: gain-based cell delay modeling Tien-Chang Hsu 1. Multilevel Large-Scale Modules Placement with Refined Neighborhood Exchange 2. Design Migration from Peripheral ASIC Design to Aera-IO Flip-Chip Design by Chip I/O Planning and Legalization anna: Speeding Up Static Timing Analysis With Crosstalk: Discrete Coupling Model Centric Approach -------- enorm: (志願1) Formal Presentation of Two Initial Variable Ordering (志願2) A Novel Heuristic for Constructing Hexagonal Steiner Trees for Routing in VLSI indark: 1. Investigation of dynamic power consumption reduction in FPGAs 2. Multilevel Large-Scale Modules Placement with Refined Neighborhood Exchange 3. Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization Akilae: (你選到老闆指定給planet的了, 再挑一篇吧 XD) jinli: A Linear Time Complexity Current Path Analysis Algorithm for ESD Protection hyliu: 1) Modified Simulated Annealing Algorithm for Large Temperature Set Applications – Simulation of VLSI Floor Planning System 2) Tapping Point Numerical Search for Exact Zero-Skew RLC Clock Tree Construction 3) Automatic Low Power Optimizations during ADL-driven ASIP Design --

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