paper ID: 286 The authors present an algorithm to minimize the mean and variance of leakage power under statistical timing constraints by sizing gate length and gate width and selecting vt, which are modeled by biased normal random variables. The problem is solved using a existed nonlinear programming package. They derived the formulas for calculating expectation and variance of whole chip leakage power. Assume that the delay of each cell is i.i.d normal random variable and the variance is proportion to the mean, they use an expectation formula to estimate the probability of satisfying the timing constraints. The experiment is performed on a simple NAND circuit. 1. The contribution of this paper is taking the effective channel length (Leff) in to consideration and showing the significance of combining Leff sizing. 2. In 4.2 delay model, the authors assume the delay is normal distributed to simplify the problem, but in fact, the normal distributed variables and the expectation equation 15 show that the delay is not normal. Therefore the probability estimation is incorrect (Equation 14). The assumption of the variance is proportion to the mean of the delay of a gate is also far-fetched. Figure 3 only shows that the mean of delay calculation is accurate. It does not show any information about the fidelity of assumption of the delay or the variance. 3. In the reviewers' opinion, there number of available vt is not that many as in this paper. The low-k process provides only two selections of vt. 4. The circuit for experiment is too simple and no runtime is reported. The reviewers suggest that the authors should test the algorithm on more complicated circuits to show the robustness and efficiency of the algorithm. 5. There are some unmatched parenthesis, for example, the "N(0, sigma^2(Vt0))" between Equation (5) and (6). -- 人生有三次機會，一個不知道什麼時候，一個已經過了，一個在未來 --

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