Since manufacturability is an important problem in nanometer technology, this paper presents a cell placement methodology to reduce the computational cost of OPC from linear dependence upon the chip area to linear with the number of distinct cell types used in the design. The simple and clear concept of the placement methodology is to place cells in regular structures. However, there are four problems based on this concept. 1. The methodology does not consider the main issues of traditional placement problems, e.g. wirelength and congestion. 2. The main problem of OPC occurs on interconnects. However, this paper just considers the computation cost of OPC by cells and does not consider the cost of OPC by interconnects. Since regular placements cannot guarantee regular wiring structures, the reduced computation cost of OPC by regular structures may useless for final layout. 3. This paper defines all regular matrix elements with the same height and width, implying that all cells have the same height and width. In practice, it is impossible that all cell types in a cell library have the same width. 4. The amplitude of OPC effect is related to the distance of two objectives. Since different cells may have different widths, it may not reasonable to assume that the OPC effect is just affected by adjacent elements in x-axis. For keeping completeness, authors should report all of the IBM-PLACE benchmarks (IBM01~IBM18) in their experimental results. Besides, please check your paper carefully, since there are some typos in your paper. For example, "OPC is a [computational] process..." in the 4th paragraph in Section 1 and "... position corresponding [to] the ..." in the item 6 in Section 3.5. -- --

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