我竟然忘了把自己排進去互評系統名單~ 請有空的人幫我看一下嚕~ 也歡迎其他人一起貼出來互相觀摩~ ================================================= This paper proposes three techniques to enhance the readability of the complicated higher level diagrams. Those three techniques are the vectorization of repetitive, the improved feedback loop breaking algorithm, and the simplification of bundle net connections using flat taps. Authors define two sets of rules in Sections 3.2 and 3.3 to simplify the bundle net connections and increase the abstraction of circuits, respectively. However, those two sets of rules are very trivial. According to an observation which was proposed in [7], authors add a BFS before the DFS of Tarjan [1] in Section 3.1 to break the feedback loops. In Section 3.4, authors modified Yoeli's robust channel routing algorithms [8] to handle vertical ordering. Nevertheless, those two algorithms are slightly modified from previous work. In Table 1, most of gate level modules have larger symbols, segments, length, and area than system and register transfer levels. According to the results, it seems that proposed techniques cannot handle larger circuits well. Besides, please compare your results with previous work. Even though previous work focused on gate level designs, you should compare results for the four gate levels modules. Please report your running time in your results. Although the reduction ratios of symbols, segments, length, and area are important issues in this problem, fast running time is also a main issue for this problem. Finally, please check Figure 5. In the line 2 on function HorizontalOrderRec(), I do not think that the loop will terminate. Besides, I think that the symbol, n, should be f in line 10. -- --

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