課程名稱︰數位電子與數位電路 課程性質︰資工系大二必修 課程教師︰賴飛羆 開課學院：電資學院 開課系所︰資工系 考試日期（年月日）：2016/1/4 考試時限（分鐘）：120分鐘 試題 : 1.(20%) (a) A transistor has T_ox = 40nm,V_TN = 0.6V,μ_n = 500 cm^2/V‧s,L = 2μm,and W = 20μm. What are K_n and the saturated and linear region values of i_D for this transistor if V_GS = 3V? (b) The technology is scaled by a factor of 2. What are the new values of T_OX, W, L, V_TN, V_GS, K_n, and i_D? 2.(20%) (a) What is the logic function that is implemented by the gate in Fig.1? (b) What are the W/L ratios for the transistors, based on the reference inverter design of Fig.2? +2.5V ○ ｜ ┌┘ ┌│∣←——┐ ｜ └┐ ┴ ｜ ｜ ＝ Y └——┼————○ ┌——┴——┐ ┌┘ ┌┘ A ○┤｜ B ○┤｜ → → ｜__________│ ┌┘ ┌┘ C ○┤｜ D ○┤｜ → → ｜__________｜ ┌┘ ┌┘ E ○┤｜ F ○┤｜ → → ｜__________│ ┴ ＝ Fig.1 +2.5V ○ ｜M_L 2/1 ┌┘ ┌│∣←—————┐ ｜ └┐ ┴ ｜ ｜ υ_O ＝ └——┼——○ ┌┘ υ_1 ○┤｜ M_S 3/1 → ｜ ┴ ＝ Fig.2 3.(20%) What are the rise time, fall time, and average propagation delay for a symmetrical CMOS inverter with (W/L)_N = 2/1, (W/L)_P = 5/1, V_DD = 2.0V , K_p' = 4*10^-5 A/V^2, K_n' = 10^-4 A/V^2, V_TN = 0.6V, V_TP = -0.6V, and C = 0.40 pF? 4.(20%) Calculate the number of transistors required to implement a 8-bit column decoder using NMOS passtransistor logic. 5.(20%) What are Noise Margins? Please draw the voltage transfer characteristic(VTC) of an inverter and give the definitions of NM_L and NM_H. 6.(20%) How did Alan Turing break the cipher code of Germany? --------------------------------------------------------------- K_n = K'_n (W/L) , K'_n = μ_nC"_OX, C"_OX = ε_OX/T_OX K_p = K'_p (W/L) , ε_OX = 3.453*10^-13 F/cm i_D = K_n (v_GS - V_TN - v_DS/2)v_DS i_D = K_n/2 (v_GS - V_TN)^2 Rise and fall times τ_PLH = 1.2 R_onP C, t_r ～= 3τ_PLH τ_PHL = 1.2 R_onN C, t_f ～= 3τ_PHL R_onN = 1/(K_n｜V_GSn - V_TN｜), R_onP = 1/(K_p｜V_GSp - V_TP｜) --

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