課程名稱︰虛擬機器 課程性質︰選修 課程教師︰徐慰中 開課學院：電資學院 開課系所︰資工所、網媒所 考試日期（年月日）︰2015.03.19 考試時限（分鐘）： 試題 : To implement an emulation system, we have the following possible choices: A) Interpretation B) Threaded interpretation C) Static binary translation D) Dynamic binary translation 1) Which one is the fastest method if the guest code has no loops and runs only once. A) B) C) D) 2) Which one can emulate faster if the guest code has many loops with large iteration counts A) B) C) D) 3) Which one may have tough challenges when the guest ISA has variable length instructions? A) B) C) D) 4) Which one may have difficulties if the guest code can modify its instructions on-the-fly (e.g. SMC). A) B) C) D) 5) Which one is often used in process virtual machines for ISA migration. A) B) C) D) 6) In BT, which of the following methods can speed up the processing of direct branches? A) Register mapping B) Local address look-up cache C) Translation Chaining D) Shadow Stack 7) In BT, which of the following can speed up the processing of indirect branches? A) Indirect branch target prediction B) Indirect branch target cache C) Shadow Stack D) Branch folding 8) All indirect branch optimizations in DBT are trying to avoid A) Branch mis-predictions B) Exceptions C) Instruction cache misses D) Context switch cost 9) Which of the following BT system is the easiest? A) x86-32 to x86-64 B) MIPS to Alpha B) ARM to x86-32 C) x86 to ARM 10) To build a BT that translate x86-64 (i.e. x64) to x86-32 (IA32), which of the following are most difficult to deal with? A) Translating ADD instructions B) Translating Push/Pop instructions C) Translating Load/Store (MOV) instructions D) Register mapping DBT systems usually implement the following optimizations: A) Register mapping B) Translated code optimizations C) Translation chaining D) Indirect branch handling. 11) In your opinion, what should be the order of importance in terms of performance? A) A > B > C > D B) B > A > C > D C) A > C > D > B D) C > A > D > B 13) What tough challenges a DBT must face when translating x86-32 code to MIPS? A) Register mapping B) Condition code emulation C) Misaligned memory references D) Code discovery 14) What would be a good target architecture for ISA migration? A) machine with many general purpose registers B) machine supports condition codes C) machine supports both big endian and little endian D) machine supports FMAC (high precision FP math) 15) Which of the following tools are based on DBT? A) PIN B) QEMU C) LLBT D) Genymotion 16) Optimizations in DBT may slow down short running apps. How does HQEMU overcome this challenge? A) Doing optimizations in a separate/parallel thread B) Rely on extensive off-line profiling C) Let short running apps going thru the original fast lane D) HQEMU does not care short running apps Ans: 1) B 2) C 3) C 4) C 5) D 6) C 7) A, B, C 8) D 9) A 10) C, D 11) C 13) B, C 14) A, C 15) A, B, D 16) A, C --

※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 114.24.41.217 ※ 文章網址: https://webptt.com/m.aspx?n=bbs/NTU-Exam/M.1429941124.A.DE4.html ※ 編輯: rod24574575 (114.24.78.41), 06/13/2015 08:42:15