課程名稱︰數位系統設計 課程性質︰必修 課程教師︰歐陽明 開課學院：電機資訊 開課系所︰資訊工程 考試日期（年月日）︰2011/1/12 考試時限（分鐘）：180 是否需發放獎勵金：是 （如未明確表示，則不予發放） 試題 : 1. (Reverse Engineering) What is the counter state diagram implied by the figure below ? There are two inputs to this counter. A is asserted to enable counting. D is used to changed count direction, that is, go through the sequence in reverse order. (15%) Figure : http://i.imgur.com/jbn7SWP.png 2. (FSM design and optimization) Consider a 4-bit sequence-detecting finite state machine. The machine has a single input X and output Z. The output is asserted after each 4-bit input sequence if it consists of one of the binary strings 0110 or 1010. The machine returns to the reset state after each and every 4-bit sequence. (a) Create a "state diagram" for this 4-bit sequence detector. (5%) (b) Use "Implication Chart Method" to reduce the number of states. (5%) (c) Use the RS flip-flops to design the machine. (10%) 3. You have learned 4 types of flip-flop, D, R-S, J-K and T this semester. (a) Please implement one type of flip-flops (RS) using basic logic gates and state their truth table. (You can use AND, OR, NOT, NAND, XOR and XNOR) (10%) (b) Please design a 4-bit simple ring counter using T flip-flop. (5%) (c) Please design a 4-bit Johnson counter using R-S flip-flop. (5%) 4. Please design a counter which can count from 0 to 15 and display on a seven-segment LED display. (You can use all kinds of logic gates and flip flop) (15%) Figure : http://i.imgur.com/f2kDIq9.png 5. When you were doing your final program project (Reverse engineering, or Forward Design), what is your project ? What is your role in your project ? What is the most difficult part in your role and please describe it, then how you have solved your problem ? (10%) 6. Semi-conductor theory. We say that TSMC has the industry leading 40 nm semiconductor process technology. (a) When the poly-silicon and diffusion width is reduced by a factor of R, so are others. That is, the source-drain voltage, the length, oxide thickness (T0) all scaled by R. Please answer what is the Packing density (gates/area) ? Power/gate. gate delay (speed) in terms of R. Explain with simple explanations using the simple circuit theory (For instance, resistance, capacitance, and speed), and make your own assumptions. (10%) (b) What is Moors' Law ? If hardware chips can follow Moors's Law, can sofrware programming productivity follow it ? Why or why not ? How to match the speed of Moors' Law in modern digital system design ? (Hint : software design vs. hardware design) (5%) (c) Current research shows that Moors' Law may reach its limit in 10 years for CMOS technology. The solution may go to multiple CPU/GPUs in one chip. What are the impacts for the students who majored in computer science ? (5%) --

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