課程名稱︰數位系統設計 課程性質︰必修 課程教師︰歐陽明 開課學院：電機資訊 開課系所︰資訊工程 考試日期（年月日）︰2010/1/13 考試時限（分鐘）：180 是否需發放獎勵金：是 （如未明確表示，則不予發放） 試題 : 1. (10%) In your opinon, how to save the budget in recent digital system products (consider the whole life cycle, from design to implementation) ? Please provide at least two approaches to save the buget. 2. (20%) (15%) (a) Design a 3-bit bidirectional counter, using only JK flip-flops. (A bidirectional counter is that when state is 000 and x = 1, it should go forward to state 001; when state is 000 and x = 0, it should go back to state 111) (5%) (b) Implement a T flip-flop only AND, OR, inverter gates, and RS flip-flops. 3. (20%) Design a circuit for calculating the answer of a binary input sequence with modular 5 (mod 5) output, using only D flip-flops, (Hint : What is the state diagram for calculating the answer of the input sequence for mod 3 ? For example, 1101 mod 3 = 1. But this question is about mod 5, more complicated) 4. (20%) There is a MN flip-flop, which (1) if MN = 00, this flip-flop's next state is 0. (2) if MN = 01, this flip-flop won't change its state. (3) if MN = 10, this flip-flop's next state is the complement of present state. (4) if MN = 11, this flip-flop's next state is 1. (a) Use present state (Q), next state (Q') and input (M, N) to construct a table. (Notice : use don't care term as possible as you can). (b) Use derive table and K-Maps to design a counter which consists of three MN flip-flops, and it's output sequence is as below: ABC = 000, 010, 001, 100, 110, 000, 010, ... (c) If your counter starts from unsigned state, what will happen ? 5. (5%) In yout programming assignment (team work) for design or reverse engineering, which part of your program is considered most time-consuming when you designed your codes ? Based on the demos of your coding in order to improve your results ? 6. (20%) (10%) (a) Please find a minimum-state table that can replace the seven-state table given below. Assume that A is the initial (reset) state. (10%) (b) Just use the RS flip-flops to design the machine. ┌──────┬────────┐ │ │Present input x │ │ │ 0 1 │ ├──────┼────────┤ │ A│ B,0 A,1 │ │ B│ C,1 D,0 │ │Prensent C│ E,1 C,1 │ │ state D│ A,1 D,0 │ │ E│ E,1 C,1 │ │ F│ F,0 G,1 │ │ G│ G,1 F,0 │ └──────┴────────┘ 7. (5%) When comparing the Mealy and Moore machines, which one or two are asychronous ? If it is asychronous, how to make it synchronous by simply modifying the logic design slightly ? --

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