課程名稱︰積體電路設計 課程性質︰電機系選修 課程教師︰盧奕璋 開課學院：電資學院 開課系所︰電機工程學系 考試日期（年月日）︰2008/4/23 考試時限（分鐘）：120 (9:10~11:10) 是否需發放獎勵金：是 （如未明確表示，則不予發放） 試題 : (1) (a) Please draw the waveform of the following input: Vclk clk gnd PULSE 0 1 0ps 100ps 100ps 400ps 1000ps (b) Please write a SPICE deck to measure rise time of a node N(the rise time defined here is a waveform to rise from 30% to 70% of its steady-state value.) (c) Please explain what does the SPICE deck mean: .param dxl=aunif(0,10nm) dxw-aunif(0,10nm) + dvthn=agauss(0,0.015,1) dvthp=agauss(0,0.016,1) .tran 1ps 1ns SWEEP MONTE=2000 (d) Please write a SPICE deck to measure instantaneous and average power delivered by a voltage source. (e) Please write a SPICE deck to find an optimized value, k, within the range from 2 to 8, to minimize the parameter delay(you can pick an initial guess by yourself). Set the number if iterations to be 20, and the transient output is recorded from 0ns to 1ps. (2) ＿＿＿＿＿ (a) Sketch a static CMOS compound gate fr the function Y=A˙B+C˙D (AOI22) at transistor level, assuming that input B always arrives late. (b) Sketch a stick diagram for the circuit in (a) and estimate the cell size. (c) what are the logical efforts and parasitic delay of AOI22(static CMOS). (d) use domino circuit to implement the function Y=A˙B+C˙D. Sketch the circuit transistor level. (e) what is the non-inverting issye of domino circuit? (f) Use AOI22-INV(static CMOS) to implement the function : Y=A˙B+C˙D. In this case, you are allowed to use larger AOI22 and INV to minimize the delay. Assume that each input can present a maximum of 30λ of transistor width. The output is to drive a load of 120λ of transistor width. Calculate the minimum path delay. (3) (a) Why substrate contacts are needed in layouts? What is body effect? (b) Draw a layout of a static CMOS inverter using either λ-rules provided in tht text book or CIC-rules used in the Homework #2. Label the dimension. (c) Please briefly explain the beta ratio effect of a static COMS inverter. (d) What are the definitions of noise margin? (4) (a) A 180nm standard cell process can have an average switching capacitance of 150pf/mm^2. You are synthesizing a chip composed of random logic with an average activity factor of 0.1. Estimate the power consumption of your chip if it has an area of 70mm^2 and runs at 450MHz at Vdd=0.9V. (b) Refer to the figure below. Show the RC model you would use to find the delay from A rising to B falling when Sel_A is high. Assume that no diffusions are shared, all transistors are 4:2, and ignore all wire capacitance. Please clearly indicate what capacitance and resistence you are modeling. --

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