課程名稱：計算機組織與結構 課程性質：必修 課程範圍：第一至第四章 開課教師：徐國偉 開課學院：理學院 開課系級：資科三 考試日期(年月日)：2012/11/23 考試時限(Mins)：3小時 附註： 可以帶計算機 (能不能帶字典我忘了,好像可以?) 試題本文： Q1.[25 points] Choose the best answer for each of the following multiple choice questions. Justify your answers when necessary. 1. Which one of the following descriptions is correct? (a) An instruction is a command that computer hardware understands and obeys. (b) An assembly language is a symbolic representaion of machine instructions. (c) A machine language is a binary representation of machine instructions. (d) All of the above. (e) None of the above. 2. Which one of the following descriptions about instruction set architecture (ISA) is true? (a) It is an abstract interface between the hardware and the lowest-level soft- ware that encompasses all the information necessary to write a machine language program that will run correctly. (b) It allows computer designers to talk about functions independently from the hardware that performs them. (c) Maintaining it as a constant enables many implementation of that archi- tecture - presumably varying in cost and performance - to run identical soft- ware. (d) All of the above. (e) None of the above. 3. Which one of the following descriptions about how the hardware and software affect performance is true? (a) All algorithm, programming language, compiler, and instruction set archi- tecture may affect instruction count. (b) All algorithm, programming language, compiler, and instruction set archi- tecture may affect CPI (clock cycles per instruction). (c) Only instruction set architecture affects clock rate. (d) All of the above. (e) None of the above. 4. Which one of the following descriptions about performance is true? (a) Execution time is the only valid and unimpeachable measure of performance. (b) We should always expect the imporvement of one aspect of a computer to in- crease overall performance by an amount proportional to the size of the im- provement. (c) We should always measure performance based on one of clock rate, in- struction count, or CPI; that is, we should always use a subset of the perfor- mance equaation as a performance metric. (d) All of the above. (e) None of the above. 5. Which one of the following descriptins about instructions is true? (a) More powerful instructions mean higher performance. (b) Write in assembly language to achieve the highest performance. (c) The importance of commercial binary compatibility means successful instuction sets do not change. (d) All of the above. (e) None of the above. Q2. [10 points] The figure given below is the abstraction of the organization of a computer discussed in class, showing the five classic components of a com- puter. What are they (1, 2, 3, 4, and 5 in the figure) respectively? You need to clarify which one is which. (請參考課本的圖,即有input、output、datapath、memory的圖,每章一開始的那張圖) Q3. [10 points] Consider two different implementations of the same instruction set architecture. There are four classes of instructions, A, B, C, and D. The clock rate and CPI of each implementation are given in the following table. --------------------------------------------------------------------------- | Implementation | Clock rate | CPI Class A | Class B | Class C | Class D | --------------------------------------------------------------------------- | P1 | 1.5 GHz | 1 | 2 | 3 | 4 | --------------------------------------------------------------------------- | P2 | 2 GHz | 2 | 2 | 2 | 2 | --------------------------------------------------------------------------- Given a program with 1000000 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C and 20% class D. What is the weighted average CPI for each implementaion? What is the execution time for each implementation? Please show all your work to support your answers for this question; answers without supporting work will earn no points. Q4. [20 points] The following table shows the number of instructions for a program. ----------------------------------------- | Arith | Store | Load | Branch | Total | ----------------------------------------- | 500 | 50 | 100 | 50 | 700 | ----------------------------------------- Assuming that Arith instructions take 1 cycle, Load and Store 5 cycles and Branch 2 cycles, what is the execution time of the program in a 2 GHz processor and what is the CPI for the program? If the number of load instructions can be reduced by one-half, what is the speed-up and what is the new CPI? Please show all your work to support your answers for this question; answers without sup- porting work will earn no points. Q5. [10 points] Hexadecimal (base 16) is commonly used numbering system for representing values in computers. Consider the following two hexadecimal num- bers: A is 0D32 and B is DD17. What is the num of A and B if they represent un- signed 16-bit hexadecimal numbers? What is the sum of A and B if they repre- sent signed 16-bit hexadecimal numbers stored in sign-magnitude format? The results should be written in hexadecimal. Please show all your work to support your answers for this question; answers without supporting work will earn no points. Q6. [10 points] The following C procedure swaps array elements. void swap (int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } Below is the ARM asssembly code segment for the above C procedure. Assume that the first argument (the address of v) is in r0, the second argument (the index k) is in r1, the local variable is in r2, the temporary for v[k+1] is in r3, and the address of v[k] is in r12. Please fill in the blanks. swap: ADD r12, r0, r1, _________ LDR r2, [r12, #0] ADR r3, [r12, #4] STR ______, [r12, #0] STR ______, [r12, #4] MOV pc, lr The following C procedure sorts array elements by using the above C procedure. void sort ( int v[], int n ) { int i, j; for (i=0; i<n; i+=1) { for (j=i-1; j>=0 && v[j] > v[j+1]; j-=1) { swap(v,j); } } } Below is the ARM assembly code segment for the above C procedure. Assume that the first argument (the address of v) is in r0, the second argument (the index n) is in r1, the local variable i is in r2, the local variable j is in r3, a copy of v[j] is in r4, a copy of v[j+1] is in r5, a copy of v is in r6, a copy of n is in r7, and the address of v[j] is in r12. Please fill in the blanks. sort: SUB sp, sp, #20 STR lr, [sp, #16] STR r7, [sp, #12] STR r6, [sp, #8] STR r3, [sp, #4] STR r2, [sp, #0] MOV r6, r0 MOV r7, r1 MOV r2, #0 for1tst:CMP r2, r1 BGE ______ SUB r3, r2, #1 for2tst:CMP r3, #0 BLT ______ ADD r12, r0, r3, ______ LDR r4, [r12, #0] LDR r5, [r12, #4] CMP r4, r5 BLE ______ MOV r0, r6 MOV r1, r3 BL ______ SUB r3, r3, #1 B ______ exit2: ADD r2, r2, #1 B ______ exit1: LDR r2, [sp, #0] LDR r3, [sp, #4] LDR r6, [sp, #8] LDR r7, [sp, #12] LDR lr, [sp, #16] ADD sp, sp, #20 MOV pc, lr Q7. [15 points] Consider the classic 5-stage pipeline in MIPS. The table given below shows the operation times for major functional units and also the time required for each instruction calss. We assume that the multiplexors, control unit, PC accesses, and sign extension unit have no delay, and also that all pipeline stages take a single clock cycle. Compare nonpipelined (single-cycle) and pipelined designs based on their execution of three load word instructions given below. We assume that both use the same hardware components. ---------------------------------------------------------------- | Instruction class | IF | ID | ALU | MEM | WB | ---------------------------------------------------------------- | Load word | 200 ps | 100 ps | 200ps | 200ps | 100 ps | lw $1, 100($0) ---------------------------------------------------------------- | Store word | 200 ps | 100 ps | 200ps | 200ps | | lw $2, 200($0) ---------------------------------------------------------------- | R-format | 200 ps | 100 ps | 200ps | | 100 ps | lw $3, 300($0) ---------------------------------------------------------------- | Branch | 200 ps | 100 ps | 200ps | | | ---------------------------------------------------------------- What is the clock cycle time for nonpipelined design, and what is that for pipelined design? What is ethe speed-up from pipelining? What is the total exe- cution time for the three instructions for nonpipelined design, and what is that for pipelined design? Please show all your work to support your answers for this question; answers without supporting work will earn no points. 選擇題答案: DDDAE --

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