作者lazyox (毅)
看板KS94-312
標題借放
時間Fri Dec 7 11:56:04 2007
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity COW is
port(clk: in std_logic;
eoc:in std_logic;
sta:out std_logic;
ale:out std_logic;
mode:in std_logic;
reset:in std_logic;
d:in std_logic_vector(7 downto 0);
out_y:out std_logic_vector(7 downto 0);
out_x:out std_logic_vector(7 downto 0);
con:out std_logic_vector(4 downto 0)
);
end COW;
architecture stru of COW is
signal counter:std_logic_vector(4 downto 0);
signal temp,tempQ:std_logic;
signal x,y:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if reset='0' then
sta<='0';
ale<='0';
out_x<="00000000";
out_y<="00000000";
con<="00000";
else
if eoc'event and eoc='1' then
if mode='1' then
x<=d;
y<=y;
else
y<=d;
x<=x;
end if;
end if;
if eoc='1' then
if clk'event and clk='1' then
counter<=counter+1;
if counter="01111" then
temp<='1'; --temp=ale
--counter<="00000";
else
temp<='0';
end if;
if temp='1' then
tempQ<='1'; --tempQ=sta
else
tempQ<='0';
end if;
end if;
else
counter<="00000";
if clk'event and clk='1' then
tempQ<='0';
end if;
end if;
end if;
ale<=temp;
sta<=tempQ;
out_x<=x;
out_y<=y;
con<=counter;
end process;
end stru;
--
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※ 編輯: lazyox 來自: 61.223.210.220 (01/10 00:26)