前年交大有題關於page replacement的考古題如下： Consider a two-level page table scheme. A 16 bit logical address is divided into a 4 bits of outer page number and 4 bits of inner page number and 8 bits of page offset. If we declare the two-dimensional array: A: int A[][] = new int[10][256]; where A[0][0] is stored at location 0x06FE, in the above paged memory system. A small process resides at location 0x7000 for manipulating the A matrix; thus every instruction fetch will be from the page with the process code location. Assume the process contains only one page of instructions. The code is as follows: for (int j=0; j < 5; j++) for (int i=0; i< 5; i++) A[i][j] = 0; Each integer contains 4 bytes. Assume i and j are register variables and only references of A[i][j] and instruction fetch will access memory. The page frame 1 has the process in it, and the other are initially empty. (Assume 3 instruction fetches for the each nested loops) a. (20%) How many page faults would occur for the following replacement algorithms, assuming one, two, three, four, five, six, and seven frames? 1. FIFO replacement 2. Optimal replacement 3. LRU replacement 4. Second-chance replacement b. (5%) Please draw the content of the two-level page table after the above access sequence. (FIFO, seven frames) c. (5%) If we set working-set window to Δ = 4 memory references, please determine the working set at the 10th memory reference and 20th memory reference. {0x07,0x70},{0x0E,ox0F,0x70} d. (5%) Assume the paging disk has an average access and transfer time of 20 milliseconds. The page tables are in main memory, with an access time of 1 microsecond per memory access. We also add a TLB, with search time of 20 nanoseconds. Assume that 80 percent of the accesses are in the TLB, what is the average effective memory access time for FIFO replacement with four frames? 請問版上有高手會解這爆氣的題目嗎 我琢磨很久還是毫無頭緒 麻煩版上的大大開導一下 ^^ --

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