[開課學院]: 資電學院 [開課系所]: 資訊系 [課程名稱]: 計算機結構學 [老師名稱]: 張貴忠 老師 [開課學期]: 981 [類型]: 98-1期末考 1.(Pipelining-25%)Branch in simple five-stage pipeline (a)Name five typical pipeline stages in an instruction cycle. (b)Explain how the branch penalty can be reduced to 2 cycle? (c)Explain how the branch penalty can be reduced to 1 cycle? (d)What are the required cost in order to achieve the solution of 1 cycle penalty? (e)What are the software solutions to eliminate the branch penalty? 2.(Pipelining-20%)We have a program core consisting of five conditional branch .The program core will be executed thousands of times.Below are the outcomes of each branch for one execution of the program core(T for taken, N for not taken). Branch 1：T-T-T-T Branch 2：N-N-N-N Branch 3：T-N-T-N-T-N Branch 4：T-T-T-N-T Branch 5：T-T-N-T-T-N-T Assume the behavior of each branch remains the same for each program core execution. For dymanic schemes, assume each branch has its own prediction buffer and each buffer initialized to the same state before each execution. List the predictions for the following branch prediction schemes: (a)Always taken (b)Always not taken (c)1-bit predictor, initialized to prediction taken (d)2-bit predictor, initialized to weakly predict taken. 3.(Cache Design-25%) (a)[15%]For a 4KB cache with a block of 16 bytes, draw the whole cache structures for direct-mapped and four-way set associative respecively for 32-bit input address. (b)[5%]Split the 32-bit address into "tag","index",and "offset" pieces.How many address bits comprise each piece for each structure? (c)[5%]Compute the total bits(including tags and one valid bit) required for these two structures respectively. 4.(Memory Hierarchy-10%)A new processor can use either a write-through or write-back cache selectable through software. (a)Assume the processor will run data intensive applications with a large number of load and store operations. Explain which cache write policy should be used. (b)Consider the same question but this time for a safety critical system in which data integrity is more important then memory performance. 5.(Data Path & Control -20 pts)Given the simple implementation of MIPS processor, please fill the control table.(Please copy the table to your answer sheet.) ____________________________________________________________________________ | | | | | | | | | | | |Inst |RegDst|ALUSrc|MemtoReg|RegWrite|MemRead|MemWrite|Branch|ALUOp1|ALUOp2| |______|______|______|________|________|_______|________|______|______|______| | | | | | | | | | | | |R-type| | | | | | | | | | |______|______|______|________|________|_______|________|______|______|______| | | | | | | | | | | | |lw | | | | | | | | | | |______|______|______|________|________|_______|________|______|______|______| | | | | | | | | | | | |sw | | | | | | | | | | |______|______|______|________|________|_______|________|______|______|______| | | | | | | | | | | | |beq | | | | | | | | | | |______|______|______|________|________|_______|________|______|______|______| --

※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 218.170.118.214