作者gecer (gecer)
看板Electronics
標題[問題] Verilog Icarus complier include 問題
時間Fri May 19 07:33:55 2017
小弟有兩個 .v file 如下
===============abc.v======================
module abc(iclk, irst, ocnt);
input iclk, irst;
output [3:0] ocnt;
reg [3:0] ocnt;
always@(posedge iclk, posedge irst)
begin
if (irst)
ocnt <= 0;
else
ocnt <= ocnt + 1;
end
endmodule
=============abcTB.v======================
'include "abc.v";
module abcTB();
reg clk, rst;
wire [3:0] cnt;
initial begin
clk = 0;
rst = 0;
#10 rst = 1;
#10 rst = 0;
end
always #10 clk = ~clk;
abc g(clk, rst, cnt);
initial
begin
$dumpfile("abc.vcd");
$dumpvars;
end
endmodule
====================================================
在windows底下進行compile
iverilog -o main_design abcTB.v abc.v
卻得到
abcTB.v:1: syntax error
I give up.
請問iverilog 若要include module file要如何使用?
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1F：推 TripleC: filelist 05/19 12:57
2F：→ htps0763: include前面是 `這個符號 不是 ' 05/29 20:42