作者j122391086 (佐宗)
看板Electronics
標題[請益] 七段顯示器漸亮
時間Tue Jun 30 12:26:11 2009
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aaa is Port (
CLK : in std_logic;
RST : in std_logic;
SW : in std_logic;
SEG7 : out std_logic_vector(6 downto 0);
led : out std_logic_vector(7 downto 0));
end aaa;
architecture arch of aaa is
signal SWCNT : std_logic_vector(2 downto 0);
signal PWMCNT : std_logic_vector(2 downto 0);
signal DISP : std_logic;
signal leds : std_logic_vector(7 downto 0);
begin
process(RST,SW)
begin
if RST='1' then
SWCNT<="000";
elsif rising_edge(SW) then
SWCNT<=SWCNT+1;
leds<=leds+1;
end if;
end process;
process(RST,CLK)
begin
if RST='1' then
PWMCNT<="000";
DISP<='0';
elsif rising_edge(CLK) then
PWMCNT<=PWMCNT+1;
if (PWMCNT="111") then
DISP<='1';
elsif (PWMCNT=SWCNT) then
DISP<='0';
end if;
end if;
end process;
led<=leds;
process(DISP,SWCNT)
variable DISPEN : std_logic_vector(3 downto 0);
begin
DISPEN := DISP & SWCNT;
case DISPEN is
when "1111"=>SEG7<="1111110";
when "1110"=>SEG7<="0110000";
when "1101"=>SEG7<="1101101";
when "1100"=>SEG7<="1111001";
when "1011"=>SEG7<="0110011";
when "1010"=>SEG7<="1011011";
when "1001"=>SEG7<="1011111";
when "1000"=>SEG7<="1110000";
when "0111"=>SEG7<="1111111";
when "0110"=>SEG7<="1111011";
when others=>SEG7<="0000000";
end case;
end process;
end arch;
請問各位 vhdl , 該如何讓0-7 變成0-9 顏色漸漸亮
本來我用這個作只能0-7 只要設定到9 就不會顯示出來
請問該改哪邊?
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