作者chasebreeze ()
看板Electronics
標題[問題] [verilog] error: Continuous assignment lval 'z' not a ne
時間Tue May 12 00:51:32 2009
QQ一直不知道怎解決這個bug
只好來請教版上各位前輩^^ 拜託了
問題：
L25: error: Continuous assignment lval 'z' not a net
Finished Phase I
Process exited with code 0.
---------程式碼---------------
module HW5_25(z,clk,rst,x,y);
input x,y,clk,rst;
output z;
reg [1:0]state;
reg z;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
always@(posedge clk or negedge rst)
if(~rst) state <= s0;
else
case(state)
s0:if(x==0&&y==1) state <= s2;
s1:if(x==0&&y==1) state <= s2;
else if (x==0&&y==0) state <= s0;
else state <= s3;
s2:if(x==0&&y==0) state <= s1;
else if(x==0&&y==1) state <= s3;
s3:if(x==0&&y==0) state <= s1;
endcase
assign z = state[1]; ------就是這一行
endmodule
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.113.93.134
1F：推 appendixisu:Z 不是保留字嗎?? 05/12 00:52
2F：推 appendixisu:阿~~assign不是要宣告成wire ?? 05/12 00:54
3F：→ chasebreeze:剛改過名稱了 還是不行>< 一樣的問題 05/12 00:54
4F：→ chasebreeze:成功了！！！ 感激不盡！！ 05/12 00:56
5F：→ chasebreeze:wire! 05/12 00:56
※ 編輯: chasebreeze 來自: 140.113.93.134 (05/12 01:02)
※ 編輯: chasebreeze 來自: 140.113.93.134 (05/12 01:02)