*SRAM circuit simulation ************************************************************************ * Library Name: SRAM * Cell Name: precharge * View Name: schematic ************************************************************************ .SUBCKT precharge b bbar *.PININFO b:I bbar:I MM1 bbar gnd vdc vdc Pch W=1.5u L=0.6u MM0 b gnd vdc vdc Pch W=1.5u L=0.6u .ENDS ************************************************************************ * Library Name: SRAM * Cell Name: mux_bitline * View Name: schematic ************************************************************************ .SUBCKT mux_bitline D7 W_E b *.PININFO D7:I W_E:I b:O MM7 net27 D7 gnd gnd Nch W=1.5u L=0.6u MM6 net5 W_E gnd gnd Nch W=1.5u L=0.6u MM5 net9 W_E gnd gnd Nch W=4.05u L=0.6u MM4 b net27 net9 gnd Nch W=4.05u L=0.6u MM3 vdd1 D7 net27 vdd1 Pch W=4.5u L=0.6u MM2 vdd1 W_E net5 vdd1 Pch W=4.5u L=0.6u MM1 net25 net27 b vdd1 Pch W=7.05u L=0.6u MM0 vdd1 net5 net25 vdd1 Pch W=7.05u L=0.6u .ENDS ************************************************************************ * Library Name: SRAM * Cell Name: sense_amp * View Name: schematic ************************************************************************ .SUBCKT sense_amp b bbar readout readoutbar sense *.PININFO b:I bbar:I sense:I readout:O readoutbar:O MM6 net42 vdd2 gnd gnd Nch W=3u L=0.6u MM5 readoutbar readout net42 gnd Nch W=1.65u L=0.6u MM4 readout readoutbar net42 gnd Nch W=1.65u L=0.6u MM3 readoutbar readout vdd2 vdd2 Pch W=2.7u L=0.6u MM2 readoutbar sense bbar vdd2 Pch W=4.35u L=0.6u MM1 readout readoutbar vdd2 vdd2 Pch W=2.7u L=0.6u MM0 readout sense b vdd2 Pch W=4.35u L=0.6u .ENDS ************************************************************************ * Library Name: SRAM * Cell Name: mux_bitbarline * View Name: schematic ************************************************************************ .SUBCKT mux_bitbarline D7 W_E bbar *.PININFO D7:I W_E:I bbar:O MM5 net4 W_E gnd gnd Nch W=4.05u L=0.6u MM4 bbar D7 net4 gnd Nch W=4.05u L=0.6u MM3 net12 W_E gnd gnd Nch W=1.5u L=0.6u MM2 bbar D7 net19 vdd3 Pch W=7.05u L=0.6u MM1 net19 net12 vdd3 vdd3 Pch W=7.05u L=0.6u MM0 net12 W_E vdd3 vdd3 Pch W=4.5u L=0.6u .ENDS ************************************************************************ * Library Name: SRAM * Cell Name: ram * View Name: schematic ************************************************************************ .SUBCKT ram A b bbar *.PININFO A:I b:I bbar:I MM5 net6 A b gnd Nch W=2.25u L=0.6u C1 b 0 0.1pf MM4 bbar A net8 gnd Nch W=2.25u L=0.6u C2 bbar 0 0.1pf MM2 net8 net6 gnd gnd Nch W=4.95u L=0.6u MM3 gnd net8 net6 gnd Nch W=4.95u L=0.6u MM1 vdd4 net6 net8 vdd4 Pch W=1.5u L=0.6u MM0 net6 net8 vdd4 vdd4 Pch W=1.5u L=0.6u .ENDS ************************************************************************ * Library Name: SRAM * Cell Name: readwrite * View Name: schematic ************************************************************************ .SUBCKT readwrite data readout readoutbar sense word_enable write_enable *.PININFO data:I sense:I word_enable:I write_enable:I readout:O readoutbar:O XI9 net13 net11 / precharge XI6 data write_enable net13 / mux_bitline XI5 net13 net11 readout readoutbar sense / sense_amp XI2 data write_enable net11 / mux_bitbarline XI0 word_enable net13 net11 / ram .ENDS .global vdd1 vdd2 vdd3 vdd4 vdc gnd vdd1 vdd1 0 5v vdd2 vdd2 0 5v vdd3 vdd3 0 5v vdd4 vdd4 0 5v vdc vdc 0 2.5v vgnd gnd 0 0v x1 data readout readoutbar sense word_enable write_enable readwrite *子電路呼 叫 *開始灌訊號 .lib 'mm0355v.l' tt *TSMC hspice model *data vdata data 0 pulse(0v 5v 0us 0.1ns 0.1ns 15us 30us) *sense vsense sense 0 pulse(0v 5v 1us 0.1ns 0.1ns 4us 15us) *word_enable vword_enable word_enable 0 pulse(0v 5v 1.5us 0.1ns 0.1ns 2.5us 15us) *write_enable vwrite_enable write_enable 0 pulse(0v 5v 8us 0.1ns 0.1ns 6us 15us) .op .option post .tran 0.1us 60us .end 這是我用cadance畫好之後輸出的檔案...SRAM的模擬 可是跑出來的波型都會有一小段突波,不曉得是哪裡出錯了?還是長寬比設計不對呢? 還麻煩高手們指引一下,謝謝 --

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