作者DecadentX (失蹤很久的鑰匙)
看板Electronics
標題[心得] verilog
時間Sat Dec 30 04:08:07 2006
寫 code 的一些心得分享
如果有 更好的 coding style 請不吝指正
其實我是想賺好文 XD
-------------------------------------------------------
counter 的寫法
reg [4:0] counter; //會變成 FF or register
wire [4:0] counter_next; //訊號線
always @(posedge clk or negedge reset)
if(~reset)
counter <= 5'b0;
else
counter <= counter_next;
assign counter_next = (enable) ? counter + 1'b1 : 0 ;
這樣可以很清楚的將 edge triage (sequental circuit)
和 level triage (combinational circuit) 分開
會比下面寫法好
always@(posedge clk or negedge rst)
if(~rst)
counter <= 5'b0;
else
counter <= counter + 1'b1;
-----------------------------------------------------------
而Final State Machine寫法也是
把 sequential 和 combinational 分開寫
* 表示會用到的變數
// Internal State REG
reg[StateSize-1:0] state;
reg[StateSize-1:0] next_state;
//FSM state assignment
//Sequental circuit
always @ (posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
/////////////////////////////////////////////
//Combinational circuit
always @( * ) begin
next_state = IDLE;
case (state)
IDLE: begin
if( * ) begin
next_state = A;
end else begin
next_state = B;
end
end
A: begin
if( * ) begin
next_state = B;
end else begin
next_state =IDLE;
end
end
B: begin
if( * ) begin
next_state = A;
end else begin
next_state =B;
end
end
default : begin
$display ("Moudle State : Error State !!");
end
endcase
end
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◆ From: 61.31.163.214
※ 編輯: DecadentX 來自: 61.31.163.214 (12/30 04:09)
1F：推 paullai:推~ 12/30 11:48
2F：推 paullai:電板也非常歡迎此類文章 ^^/ 12/30 11:52
3F：推 paullai:也歡迎大家投稿～ 12/30 11:54
4F：推 pow:"Finite State Machine" 12/30 12:29
5F：推 mouein:XD 樓上推才看到~~ 12/30 13:17
6F：推 Seals:厚 VHDL 地時代已經過去了嘛? :( 12/30 19:21
7F：推 jcboy:兩個都會不就好了嗎:)？ 12/31 23:49
8F：→ DecadentX:最後狀態機~~~XD 01/03 00:03