作者wowow11 (owo)
看板Electronics
標題[問題] verilog 問題
時間Sun May 14 21:17:58 2006
下面是一個divide的code
`define DvLen 16
`define DdLen 32
`define QLen 16
`define HiDdMin 16
module divide
(input [`DdLen-1:0] ddInput,dvInput,
output reg signed [`QLen-1:0] quotient,
input go,
output reg done);
reg signed [`DdLen-1:0] dividend;
reg signed [`DvLen-1:0] divisor;
reg negDivisor,negDividend;
always begin
done=0;
wait(go);
divisor=dvInput;
dividend=ddInput;
quotient=0;
if (divisor) begin
negDivisor=divisor[`DvLen-1];
if (negDivisor) divisor=-dividend;
negDividend=dividend[`DdLen-1];
if (negDividend) dividend=-dividend;
repeat (`DvLen) begin
quotient=quotient<<1;
dividend=dividend<<1;
dividend[`DdLen-1:`HiDdMin]=
dividend[`DdLen-1:`HiDdMin]-divisor;
if (!dividend[`DdLen-1]) quotient=quotient+1;
else
dividend[`DdLen-1:`HiDdMin]=
dividend[`DdLen-1:`HiDdMin]+divisor;
end
if (negDivisor != negDividend) quotient=-quotient;
end
done=1;
wait(~go);
end
endmodule
教授要我們寫出一個4種狀況的test bench (正除正 正除負 負除正 負除負)
以下是我寫的code
`include "3.1.v"
module test_divide;
reg [`DdLen-1:0] dvInput,ddInput;
reg go;
wire done;
wire [`QLen-1:0] quotient;
parameter DELY = 100;
always begin go=1; forever #(DELY/2) go=~go; end
divide t (ddInput,dvInput,quotient,go,done);
initial begin
ddInput=16'd0;dvInput=16'd0;
#DELY go=1'b0; ddInput= 16'd8; dvInput= 16'd2;
#DELY go=1'b0; ddInput= -16'd4; dvInput= 16'd2;
#DELY go=1'b0; ddInput= 16'd2; dvInput= -16'd2;
#DELY go=1'b0; ddInput= -16'd9; dvInput= -16'd3;
#DELY $stop;
end
initial $monitor($time,,,"ddInput=%d dvInput=%d,quotient=%d",ddInput,dvInput,quotient);
endmodule
在執行正除正沒問題 可是負數就出現一堆數字了 希望各位大大幫我更正一下QQ
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1F：推 tkhan:太深奧看不懂，只能確定一件事，此電路不可合成.. 05/14 22:28
2F：→ wowow11:簡單說就是我要做8除2 -4除2 2除-2 -9除-3 但只有8除2正常 05/14 22:53
3F：→ wowow11:其他有負數的都出現一堆數字orz 05/14 22:54