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標 題VHDL改到卡住,可否幫個忙..
發信站清華資訊(楓橋驛站) (Mon Apr 10 00:09:52 2006)
轉信站ptt!ctu-reader!ctu-peer!news.nctu!news.cis.nctu!news.cs.nthu!netnews.c
這是 4位元除法器
下面是我自己寫的程式,從MODELSIM模擬可以看出與實際想要的有一點差距...
改了兩天,還是沒辦法實現,可能功力還不夠,改不出來了~~
想請高手幫我看看,哪邊觀念錯了,所以得不到想要的~
這不是學校作業,只是拿個題目寫看看,誰知道就卡住了.../.\
http://photo.pchome.com.tw/fpga/114459864524/
=======================================================================
entity SAS is
Port ( CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0);
R : out STD_LOGIC_VECTOR (3 downto 0);
START : in STD_LOGIC);
end SAS;
architecture Behavioral of SAS is
signal cnt : integer range 0 to 3:=3;
signal A_reg : std_logic_vector (7 downto 0):="00000000";
signal Q_reg : std_logic_vector (3 downto 0):="0000";
signal R_reg : std_logic_vector (3 downto 0):="0000";
signal sel :std_logic_vector (1 downto 0):="00";
begin
process(CLK,sel)
begin
if (CLK'event and CLK = '1') then
if START = '1' then
Q <= "0000";
R <= "0000";
sel <= "00";
end if;
case sel is
when "00"=>
A_reg<="0000" & A;
sel <= "01";
when "01"=>
A_reg(7 downto 0) <= A_reg(6 downto 0) & '0';
if A_reg(7 downto 4) >= B then
A_reg(7 downto 4) <= A_reg(7 downto 4) - B;
Q_reg(cnt) <= '1';
cnt <= cnt - 1;
else
A_reg(7 downto 0) <= A_reg(6 downto 0) & '0';
Q_reg(cnt) <= '0';
cnt <= cnt - 1;
end if;
if cnt = 0 then
sel <= "10";
else
sel <= "01";
end if;
when "10"=>
Q <= Q_reg;
R <= A_reg(7 downto 4);
when others=>
null;
end case;
end if;
end process;
end Behavioral;
--
※ Origin: 楓橋驛站<bbs.cs.nthu.edu.tw> ◆ From: 210-58-7-53.cm.dynamic.apol.com.tw