綜合同學的問題以及我自己 implement 時發現 spec 的缺失， 我對 spec 做了一些補充與修改。 請仔細閱讀，change logs 貼在本文的最後， 如果造成已經先 implement 的同學的不便，敬請見諒。 不過大部分的改變都是要讓 implementation 以及我們的批改容易一點。 請至 ceiba 區的課程公佈欄下載， 由於 ceiba 不能在一個公告張貼多重檔案，所以分成兩個公告 (word, pdf) 我還沒有把它們上加到 fraig.tgz (作業區) 裡， 等我改好 code 加上 testcases 之後再一起 update. [01/03/2011] v0.3 * Spec correction: Updated the list of detected errors and their corresponding error messages. (1-1) * Spec change: Add another floating gate case: “(d) A gate with a floating fanin”. (1-2) * Spec clarify: Explain how the DFS list is constructed. (1-3) * Spec change: Floating gates of case (b) should be included in the DFS list. (1-3) * Spec addition: Constant gate (i.e. CONST0) should also be included in DFS list if it is visited during DFS traversal. (1-3) * Spec addition: Comments on circuit optimization. (1-4) * Spec addition: Perform strash only on gates in the DFS list. (1-5) * Spec addition: When a merge operation is to be performed, retain the gate with the smaller ID. (1-6) (1-10) * Spec change: Allow space characters before and after a simulation input pattern. But, still, no space character is allowed between the input assignments in a pattern (1-8) * Spec addition: Message for the erroneous simulation patterns. (1-8) * Spec addition: Add error message on command errors. (2-2) * Spec clarify: “CIRPring -Netlist” only prints the gates in DFS list. “ Cir -fec” only reports the currently identified and unproven FEC pairs. (2-2) * Spec addition: Add ‘*’ for the floating (undefined) fanin in the “ CIRPrint -Netlist” command. (2-2) * Spec clarify: Constant 0 should be reported as “CONST0” be “cirp -n”. (2-2) * Spec change: Change the floating gate message (for “cirp -fl”) to “ Gates with floating fanin(s):” and “Gates defined but not used :”. (2-2) * Spec addition: Add “UNDEF” for undefined fanins in the “CIRGate -fanin/-fanout” command. (2-3) --

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