※ [本文转录自 Electronics 看板] 作者: gulit (gulit爱maplefcc) 看板: Electronics 标题: 宏太科技 Embedded Memory, DFM, IP Verification 产品研讨会(1.24) 时间: Wed Jan 17 12:38:03 2007 宏太科技 敬邀您出席 Embedded Memory, DFM, IP Verification 产品研讨会 时间 : 2007年1月24日(星期三) 下午1:00 -- 5:30 地点 : 新竹科学园区科技生活馆202室 (新竹科学园区工业东二路1号) 费用 : 免费入场，备有茶点 主办单位 : 宏太科技 (Avant Technology Inc., http://www.avant.com.tw) 协办单位 : 台湾SoC推动联盟 (Taiwan SoC Consortium) 报名 : 请至 http://www.avant.com.tw/chinese/seminar.htm 完成报名手续 抽奖 : 参加者有机会抽中高级数位相机一台, 请携带名片参加抽奖 研讨会议程 演讲主题 演讲摘要 13:00 –13:30 Registration 　 13:30 –14:20 Architectural considerations for cool designs: Strategies and implementation techniques for embedded memory IPs to minimize power consumption and achieve the most optimum performance and cost Cyrus Afghahi, CEO, Novelics Farzad Zarrinfar, President, Novelics The rapid expansion of feature-sets in consumer products such as cell phones and portable multimedia solutions is pushing the limits of embedded memories. Price pressure, the need for differentiated features with balanced power/performance, data security, and dealing with minimum IP suppliers are forcing chip designers to evaluate emerging memory techniques for their designs. This section introduces compiler-driven 'Cool' and 'zero-leakage' Memory IPs include coolSRAM-1T, coolSRAM-6T, coolOTP, coolReg, coolCache, coolCAM and coolROM for low power, and high performance ASICs, ASSPs, and SOC designs. These IPs are implemented with standard logic CMOS process with no additional masks or process steps to minimize cost, as well as maximize reliability and portability. 14:20 –15:10 Manufacturing Induced Variation Aware Design In 130nm And Below -DFM/DFY- Darren M. Tay President/CEO, Nanno SOLUTIONS Won-Young Jung Executive VP/CTO, Nanno SOLUTIONS As scale goes down to 130nm and below, interconnect is getting more dominant and significant for design performance. However, designers consider device worstcase models for both verification and characterization of circuit performance. They typically do not include interconnect worstcase model in their analysis because the impacts of interconnect related process variations cannot be decided in worstcase model. Recent efforts have been attempted in determining interconnect, worstcase of statistical approaches. Despite of the efforts, these methods fail to accurately predict an interconnect worstcase model, which has non-normal distribution, and the methods are time-consuming when used to generate the models. This seminar will discuss a new design environment to provide the interconnect worstcase model/DB based on a statistical algorithm with accuracy and efficiency. It will also introduce state-of-art DFM/DFY solutions which are provided by Nanno SOLUTIONS, Inc. 15:10 –15:30 Coffee Break 　 15:30 –16:20 Bridging The Verification Gap Stephen Scholefield CEO, TransEDA Coverage Analysis in the Design Flow Practical Value of Coverage Analysis Coverage Measurements and their Practical Value Practical Coverage Directed Verification Methodology Managing and Optimizing the Test Suite Case Study 16:20 –17:10 SoC设计的自动化验证 Thalia Ko Manager, 宏太科技 以Assertion为基础形式验证是一种常用来对SoC数位电路进行功能验证的方法。与动态 式的解决方案相较，虽然此一技术具有多项优势，但也有一些缺点，使其只能局限於具备 验证专业知识的专家所使用。因此，为使形式验证能发挥更佳的效益，业界致力於将其予 以自动化作业以及与模拟技术平滑整合。 Aerielogic将展示以下几个功能验证领域是可以透过自动化形式验证来取得更大的效益： 设计覆盖增强、协议相容检查，以及功能效能分析。利用Aerielogic的设计方法，不论是 设计人员或验证工程师都可以轻松地达成这些工作。 17:10 抽奖:数位相机 　 敬请各位业界先进拨冗参加，谢谢! --

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※ 发信站: 批踢踢实业坊(ptt.cc) ◆ From: 210.68.183.71