各位好 我们有一个题目是写 Please design a circuit to detect the sequence 1101. A sequence detector produces out = 1 if the consecutive input signals are 1101; otherwise, out = 0.For example, example 1 -----------|.....|-------|.....|------- in : 0,0,0,1,1,0,1,1,0,0,1,1,0,1,0,0... out: 0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,0... .................^.............^......... example 2 -----|.....|.....|------------- in : 1,1,0,1,1,0,1,0,0,0,1,0,0... out: 0,0,0,1,0,0,1,0,0,0,0,0,0... ...........^.....^............... 助教给的wave图长这样 https://imgur.com/gallery/HqGtA5M 我想问的是下面这张图，有符合上面这个题目的叙述吗? https://imgur.com/gallery/iGcWcjV 因为设计成正缘触发，两张图的差异就变成了在最後一个1时 一个是0 -> 1，另一个是1 -> 0 让我搞不太清楚应该是怎麽做 刚学verilog 如果问题很模糊的话，我会再解释更清楚一点的，谢谢:) --

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