作者z701660993 (Mr.Liar)
看板PLT
标题[问题] VHDL的问题
时间Wed Dec 5 21:08:41 2007
请问要怎麽将下面的程式改写成可以累加的呢
http://www.pixnet.net/photo/z701660993/74075903
如上图 当我输入是"100"时 输出会是15
我希望能将它变成15=>30=>45 这样一直加上去
而当输入变成"000"时 输出则会维持45这个数值 而不是归零
希望有人能帮帮我这新手的问题QQ
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity A1 is
port(
I : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
C : OUT integer range 99 downto -99);
END A1;
ARCHITECTURE A OF A1 IS
BEGIN
PROCESS(I)
variable counter : integer range -99 to 99;
BEGIN
counter := 0;
if I = 000 then counter := counter+0;
elsif I = 001 then counter := counter+1;
elsif I = 010 then counter := counter+5;
elsif I = 011 then counter := counter+10;
elsif I = 100 then counter := counter+15;
elsif I = 101 then counter := counter-10;
elsif I = 110 then counter := counter-5;
elsif I = 111 then counter := counter-1;
end if;
C<=counter;
END PROCESS;
END A;
--
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