IMEC Sees Double Patterning as Next Step towards 32nm Christoph Hammerschmidt EE Times Europe 07/16/2007 3:54 PM MUNICH, Germany — At Semicon West trade fair, Belgian research institute IMEC announced progress towards 32nm lithography schemes, with double patterning emerging as a probable intermediate solution before other techniques will be in place. The institute sees significant progress in 32nm lithography development during the past year. "Driven by the needs to quickly develop 32nm processes for memory applications and based on the promising results, we are quite confident that double patterning will be taken up as an intermediate solution for 32nm half pitch before a single exposure solution is ready for production", said IMEC CEO Luc Van de hove. IMEC is driving the 32nm research in three approaches: high-index 193nm lithography, double-patterning techniques for 193nm water-based immersion lithography and Extreme Ultra Violet (EUV) lithography. In the area of double patterning, IMEC presently investigates challenges such as mask design split, more cost-effective processes, and critical dimension (CD) and overlay control. The research institute has demonstrated the potential capability to achieve sub-3nm critical dimensions, which is one of the requirements for 32nm production. IMEC simulations have shown that a more uniform wafer CD distribution can be obtained by minimizing the mean difference between the CD populations. In this context, the institute is doing research to develop techniques to split full chip designs automatically, which will be required when the double patterning technique is to be used in production environments. In collaboration with EDA vendors, IMEC researchers are investigating how double patterning will affect EDA workflows and how designs can be made split-compliant. In the immersion lithography segment, IMEC will extend its strategic partnership with ASML. While the current research at the institute is carried out on an ASML XT:1700i with a numerical aperture of 1.2, both parties now agreed to install a new XT:1900i with an NA of 1.35. According to an IMEC press release, the target of high-index immersion lithography is to drive the NA to a range of 1.55 to 1.6. This will enable to extend the 193nm immersion lithography to the 32nm half pitch node. In the field of fluids, the researchers have identified at least one fluid that seems to meet most criteria required for the technology, but they did dot elaborate. Presently, purified water is used for immersion lithography, but in order to achieve higher NA the researchers probably will have to use a different liquid. As to EUV, IMEC made it clear that this option is the only one with a clear extendibility towards 22nm and possibly beyond. During the past year, IMEC worked on integrating the ASML alpha tool with Sn EUV source. Presently, the optics are fine-tuned for high resolution image and acceptance testing. The research program so far has been focusing on interference exposures for resist preparation, design and reticle tape-out as well as EUV simulations to prepare the projects. In addition, the researchers also started to investigate how today's chemically amplified resists can be pushed down to 30nm feature sizes and below. Also at Semicon West, IMEC and semiconductor assembly and test service provider Amkor Technology also announced they will jointly develop wafer-level processing techniques aiming at 3D integration of semiconductor devices. The collaboration aims at providing advanced low-cost packaging solutions, IMEC said in a press statement. http://eetimes.eu/showArticle.jhtml?articleID=201001500&queryText=imec --

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